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參數(shù)資料
| 型號： | T7698 |
| 廠商： | Lineage Power |
| 英文描述： | Quad T1/E1 Line Interface and Octal T1/E1 Monitor(四T1/E1線接口和八T1/E1監(jiān)控器) |
| 中文描述： | 四T1/E1線路接口和八路的T1/E1監(jiān)視器（四個T1/E1線接口和八T1/E1的監(jiān)控器） |
| 文件頁數(shù)： | 75/112頁 |
| 文件大小： | 1359K |
| 代理商： | T7698 |
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Data Sheet
January 1999
T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor
75
Lucent Technologies Inc.
Frame Monitors
(continued)
Frame Monitor Parameter/Control Registers
(continued)
Frame Monitor Control Option Register (Framer_PR2)
These bits enable/disable various control/mode options.
Table 52. Frame Monitor Control Option Register (Framer_PR2)
Frame Monitor CEPT Data Link Option Register (Framer_PR3)
This register controls the time slot used for CEPT data link.
Table 53. Frame Monitor CEPT Data Link Option Register (Framer_PR3)
Bit
0
Description
Receive A-Bit Filter (CEPT Only).
A 0 enables the A-bit alarm on any occurrence of an A bit = 1
event. A 1 forces the occurrence of three consecutive A bit = 1 events to assert and three consecu-
tive A bit = 0 events to deassert the A-bit (RFA) alarm.
Synchronous Sa6 Monitoring (CEPT Only).
A 0 enables the asynchronous monitoring of the Sa6
codes relative to the receive CRC-4 submultiframe. A 1 enables synchronous monitoring of the Sa6
pattern relative to the receive CRC-4 submultiframe.
AIS Detection Mode (CEPT Only).
A 0 enables the detection of received line AIS as described in
ETSI Draft prETS 300 233:1992. A 1 enables the detection of received line AIS as described in ITU
Rec. G.775.
THR_Enable (All Modes).
A 1 enables the thresholds for errored seconds, bursty errored seconds,
and severely errored seconds to be programmed by writing the desired threshold to registers
Framer_PR8—Framer_PR11. A 0 selects the hardwired threshold values shown in Tables 44—46.
G.826 Mode.
A 0 forces the performance counters (errored second, severely errored second, and
unavailable state) to count the current status. A 1 forces these counters to conform to the ITU G.826
standard. A delay of ten seconds is inherent in the G.826 mode. Transition from 0 to 1 in this bit will
clear all performance counters.
Receive Frame Monitor Reframe (All Modes).
This bit should normally be 0. A 0 to 1 transition of
this bit generates a clock pulse that forces the loss of frame alignment (LFA) state and initiates a
frame alignment search. Subsequent reframe commands must have this bit in the 0 state first.
Factory Test.
This bit must always be set to 0.
Software Restart (All Modes).
This bit should be set to 0 for normal operation. Setting this bit high
forces reframe and clears internal counters, but keeps the parameter registers as programmed. This
bit must be set to 0 to deassert this state.
1
2
3
4
5
6
7
Bits
0—2
Description
Bit 2
0
0
0
0
1
Reserved.
Must be set to the 0 state.
Bit 1
0
0
1
1
0
Bit 0
0
1
0
1
0
Sa4 time slot is used for data link.
Sa5 time slot is used for data link.
Sa6 time slot is used for data link.
Sa7 time slot is used for data link.
Sa8 time slot is used for data link.
3—7
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