參數(shù)資料
型號： T7698
廠商： Lineage Power
英文描述： Quad T1/E1 Line Interface and Octal T1/E1 Monitor(四T1/E1線接口和八T1/E1監(jiān)控器)
中文描述： 四T1/E1線路接口和八路的T1/E1監(jiān)視器（四個T1/E1線接口和八T1/E1的監(jiān)控器）
文件頁數(shù)： 20/112頁
文件大?。?/td> 1359K
代理商： T7698
Data Sheet
January 1999
T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor
20
Lucent Technologies Inc.
Microprocessor Interface
(continued)
Microprocessor Interface Register Architecture
(continued)
5-4706(F).ar.6
Figure 3. T7698’s Secondary Register Bank Architecture
FRAME MONITOR MODE OPTION REGISTER
FRAME MONITOR CRC-4 MULTIFRAME CONTROL
OPTION REGISTER
FRAME MONITOR CONTROL OPTION REGISTER
FRAME MONITOR CEPT DATA LINK OPTION REGISTER
ET1 ERRORED EVENT ENABLE REGISTER
ET1 REMOTE END ERRORED EVENT ENABLE
REGISTER
NT1 ERRORED EVENT ENABLE REGISTER
NT1 REMOTE END ERRORED EVENT ENABLE
REGISTER
ERRORED SECOND THRESHOLD REGISTER
SEVERELY ERRORED SECOND THRESHOLD
REGISTER (BITS 8—15)
SEVERELY ERRORED SECOND THRESHOLD
REGISTER (BITS 0—7)
BURSTY ERRORED SECOND THRESHOLD
REGISTER
FRAME MONITOR EXERCISE REGISTER
T7698 GLOBAL INDEX REGISTER
FRAME MONITOR CRC OPTION REGISTER
FRAME MONITOR STATUS AND COUNTER REGISTER
STACK
FDL CONFIGURATION CONTROL REGISTER
FDL RECEIVER FILL LEVEL CONTROL REGISTER
FDL RECEIVER MATCH CHARACTER REGISTER
FDL TRANSPARENT MODE CONTROL REGISTER
FDL FILL STATUS REGISTER
FDL RECEIVER STATUS REGISTER
FDL RECEIVER ANSI ESF BIT CODES
RECEIVER FDL FIFO ACCESS REGISTER
RESERVED
0.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
0.
1.
2.
3.
4.
5.
6.
7.
8.—15.
T7698
FRAME MONITOR 1
REGISTER
ADR: 1101 00000001
ADR: 1101 00001000
ADR: 1101 00000010
ADR: 1101 00010001
ADR: 1101 00010010
ADR: 1101 00011000
FRAME MONITOR MAIN STATUS
REGISTER
FACILITY ALARM CONDITION
REGISTER
FACILITY REMOTE ALARM
STATUS REGISTER
LOCAL AND REMOTE NT1 FACILITY
EVENT REGISTER
FACILITY EVENT REGISTER
FACILITY ERRORED EVENT
REGISTER
FACILITY EVENT REGISTER
BIPOLAR VIOLATION COUNTER
REGISTER (BITS 8—15)
BIPOLAR VIOLATION COUNTER
REGISTER (BITS 0—7)
FRAMING BIT ERROR COUNTER
REGISTER (BITS 8—15)
FRAMING BIT ERROR COUNTER
REGISTER (BITS 0—7)
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
52.
0.
1.
2.
3.
BYTE 0
BYTE 1
BYTE 2
BYTE 3
FDL [1—8] REGISTER BANK
FRAME MONITOR STATUS AND COUNTER
REGISTER STACK
HDLC RECEIVE FIFO
T7698
FRAME MONITOR 2
REGISTER
T7698
FRAME MONITOR 8
REGISTER
T7698
FDL1 REGISTER
BANK
T7698
FDL2 REGISTER
BANK
T7698
FDL8 REGISTER
BANK
FRAME MONITOR [1—8] REGISTER BANK
0.
LOCAL AND REMOTE ET1 FACILITY
EVENT REGISTER
63.
BYTE 63
BANK
BANK
BANK
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