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參數(shù)資料
| 型號： | T7698 |
| 廠商： | Lineage Power |
| 英文描述： | Quad T1/E1 Line Interface and Octal T1/E1 Monitor(四T1/E1線接口和八T1/E1監(jiān)控器) |
| 中文描述： | 四T1/E1線路接口和八路的T1/E1監(jiān)視器（四個T1/E1線接口和八T1/E1的監(jiān)控器） |
| 文件頁數(shù)： | 15/112頁 |
| 文件大?。?/td> | 1359K |
| 代理商： | T7698 |
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Data Sheet
January 1999
T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor
15
Lucent Technologies Inc.
T7698 Device Overview
The T7698 is a four-channel device with a shared microprocessor interface. Each of the four channels consists of a
line interface unit (LIU) and two frame monitors with facility data links (FDL). The LIUs convert bipolar line data
pulses into logic level terminal data, with options for monitoring of the line integrity, clock and data recovery or raw
sliced data, timing for the data and clock recovery, jitter attenuation, equalization, zero bit coding, loopbacks, and
other functions. The frame monitors monitor line performance providing data on integrity of the frame structure,
perform cyclical redundancy checks for bit errors, and extract alarm and data link signaling for operations and
maintenance functions.
System Interface Pin Options
The system interface can be configured to operate in a number of different modes. The different modes change the
functionality of the system interface pins, as shown in Table 2. Dual-rail or single-rail operation is possible using the
DUAL control bit (register 5, bit 4). Dual-rail mode is enabled when DUAL = 1; single-rail mode is enabled when
DUAL = 0. In dual-rail operation, data received from the line interface on RTIP and RRING appears on RPD (pins
14, 38, 64, 88) and RND (pins 13, 39, 63, 89) at the system interface and data transmitted from the system inter-
face on TPD (pins 17, 35, 67, 85) and TND (pins 16, 36, 66, 86) appears on TTIP and TRING at the line interface.
In single-rail operation, data received from the line interface on RTIP and RRING appears on RDATA (pins 14, 38,
64, 88) at the system interface and data transmitted from the system interface on TDATA (pins 17, 35, 67, 85)
appears on TTIP and TRING at the line interface.
In both dual-rail and single-rail operation, the clock/data recovery mode is selectable via the CDR bit (register 5,
bit 0). When CDR = 1, the clock and data recovery is enabled and the system interface operates in a nonreturn-to-
zero (NRZ) digital format, recovering the clock and data from the incoming pulses. When CDR = 0, the clock and
data recovery is disabled and the system interface operates on unretimed sliced data in RZ data format. No clock
is recovered, freeing up the RCLK pin to be used to indicate an analog loss of signal (ALOS). If the incoming pulse
height falls below –18 dB, the ALOS pin (15, 37, 65, 87) is asserted high, and remains high until the signal rises
above –14 dB.
In single-rail mode only, B8ZS/HDB3 encoding/decoding may be selected by setting the control bits properly (see
the Zero Substitution Decoding (CODE) section, page 23, and the Zero Substitution Encoding (CODE) section,
page 31). When a coding violations occurs, the BPV pin (pins 13, 39, 63, 89) is asserted high.
Table 2. System Interface Pin Mapping
Configuration
RCLK/
ALOS
RCLK
RPD/
RDATA
RPD
RND/BPV
TPD/
TDATA
TPD
TND
Dual-rail with Clock Recovery (DUAL = 1,
CDR = 1)
Dual-rail with Data Slicing (DUAL = 1, CDR = 0)
Single-rail with Clock Recovery (DUAL = 0,
CDR = 1)
Single-rail with Data Slicing (DUAL = 0, CDR = 0)
RND
TND
ALOS
RCLK
RPD
RDATA
RND
BPV
TDATA
Not Used
ALOS
RPD
RND
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