- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383876 > T7698 (Lineage Power) Quad T1/E1 Line Interface and Octal T1/E1 Monitor(四T1/E1線接口和八T1/E1監(jiān)控器) PDF資料下載
參數(shù)資料
| 型號： | T7698 |
| 廠商： | Lineage Power |
| 英文描述： | Quad T1/E1 Line Interface and Octal T1/E1 Monitor(四T1/E1線接口和八T1/E1監(jiān)控器) |
| 中文描述： | 四T1/E1線路接口和八路的T1/E1監(jiān)視器（四個(gè)T1/E1線接口和八T1/E1的監(jiān)控器） |
| 文件頁數(shù)： | 5/112頁 |
| 文件大?。?/td> | 1359K |
| 代理商： | T7698 |
第1頁第2頁第3頁第4頁當(dāng)前第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁
Data Sheet
January 1999
T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor
5
Lucent Technologies Inc.
List of Tables
Tables
Page
Table 1. Pin Descriptions .......................................................................................................................................11
Table 2. System Interface Pin Mapping .................................................................................................................15
Table 3. Microprocessor Configuration Modes ......................................................................................................16
Table 4. MODE [1—4] Microprocessor Pin Definitions ..........................................................................................17
Table 5. Microprocessor Input Clock Specifications ..............................................................................................18
Table 6. Primary (LIU) Register Bank ....................................................................................................................19
Table 7. Register Map for CODE Bits ....................................................................................................................23
Table 8. Digital Loss of Signal Standard Select .....................................................................................................25
Table 9. LOSSD and RCVAIS Control Configurations (Not Valid During Loopback Modes) .................................25
Table 10. DS1 RLIU Specifications ........................................................................................................................26
Table 11. CEPT RLIU Specifications .....................................................................................................................28
Table 12. Equalizer/Rate Control ...........................................................................................................................30
Table 13. Register Map for CODE Bits ..................................................................................................................31
Table 14. DSX-1 Pulse Template Corner Points (from CB119) .............................................................................32
Table 15. DS1 Transmitter Specifications ..............................................................................................................33
Table 16. CEPT Transmitter Specifications ...........................................................................................................34
Table 17. Loopback Control ...................................................................................................................................39
Table 18. AMI Encoding .........................................................................................................................................41
Table 19. DS1 B8ZS Encoding ..............................................................................................................................41
Table 20. ITU HDB3 Coding and DCPAT Binary Coding .......................................................................................42
Table 21. Alarm Registers ......................................................................................................................................43
Table 22. Alarm Mask Registers ............................................................................................................................44
Table 23. Global Control Register (0100) ..............................................................................................................44
Table 24. Global Control Register (0101) ..............................................................................................................45
Table 25. Channel Configuration Registers (0110—1001) ....................................................................................45
Table 26. Channel Configuration Register (1011) ..................................................................................................46
Table 27. Control Register (1100) ..........................................................................................................................46
Table 28. Global Index Register .............................................................................................................................47
Table 29. T-Carrier Hierarchy ................................................................................................................................51
Table 30. D4 Superframe Format ..........................................................................................................................52
Table 31. DDS Channel 24 Format ........................................................................................................................52
Table 32. Extended Superframe (ESF) Structure ..................................................................................................54
Table 33. T1 Loss of Frame Alignment Criteria .....................................................................................................55
Table 34. T1 Frame Alignment Procedures ...........................................................................................................56
Table 35. Allocation of Bits 1 to 8 of the FAS Frame and the NOT FAS Frame ....................................................58
Table 36. ITU CRC-4 Multiframe Structure of the T7698 .......................................................................................60
Table 37. Red Alarm Conditions ............................................................................................................................66
Table 38. Remote Frame Alarm Conditions ...........................................................................................................66
Table 39. Alarm Indication Signal Conditions ........................................................................................................67
Table 40. Sa6 Bit Coding Recognized by the T7698 Receive Frame Monitor .......................................................68
Table 41. Sa6 Bit Coding of NT1 Interface Events Recognized by the T7698 Receive Frame Monitor ................69
Table 42. AUXP Synchronization and Clear Synchronization Process ..................................................................69
Table 43. T7698 Event Counters Definition ...........................................................................................................70
Table 44. T7698 Errored Second Counters Definition ...........................................................................................71
Table 45. T7698 Bursty Errored Second Counters Definition ................................................................................72
Table 46. T7698 Severely Errored Second Counters Definition ............................................................................72
Table 47. T7698 Unavailable Second Counter Definition ......................................................................................72
Table 48. Frame Monitor Registers ........................................................................................................................73
Table 49. Framer_PR0 Frame Monitor Mode Bits Decoding .................................................................................74
Table 50. Framer_PR0 Line Code Option Bits Decoding ......................................................................................74
Table 51. CEPT CRC-4 Option Bits Decoding .......................................................................................................74
Table 52. Frame Monitor Control Option Register (Framer_PR2) .........................................................................75
Table 53. Frame Monitor CEPT Data Link Option Register (Framer_PR3) ...........................................................75
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| T7705A | SUPPLY-VOLTAGE SUPERVISORS |
| T8100A | H.100/H.110 Interface and Time-Slot Interchanger(H.100/H.110接口和干線時(shí)間段交換機(jī)) |
| T8100 | H.100/H.110 Interface and Time-Slot Interchanger(H.100/H.110接口和干線時(shí)隙交換機(jī)) |
| T8102 | H.100/H.110 Interface and Time-Slot Interchanger(H.100/H.110接口和干線時(shí)隙交換機(jī)) |
| T8105 | H.100/H.110 Interface and Time-Slot Interchanger(H.100/H.110接口和干線時(shí)隙交換機(jī)) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T77 | 制造商:Thomas & Betts 功能描述:2-1/2"CONDUIT BODY,IRON,T,F-7 制造商:Cooper Crouse-Hinds 功能描述: 制造商:Thomas & Betts 功能描述:Fittings T-Fitting 2.5inch Non-Thread Iron |
| T7700 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Core2 Duo Processors and Core2 Extreme Processors for Platforms Based on Mobile 965 Express Chipset Family |
| T77000150 | 制造商:Assembly Value Added 功能描述: |
| T7705102CA | 制造商:Texas Instruments 功能描述: |
| T7705A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SUPPLY-VOLTAGE SUPERVISORS |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。