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參數(shù)資料
| 型號(hào)： | T7698 |
| 廠商： | Lineage Power |
| 英文描述： | Quad T1/E1 Line Interface and Octal T1/E1 Monitor(四T1/E1線接口和八T1/E1監(jiān)控器) |
| 中文描述： | 四T1/E1線路接口和八路的T1/E1監(jiān)視器（四個(gè)T1/E1線接口和八T1/E1的監(jiān)控器） |
| 文件頁數(shù)： | 80/112頁 |
| 文件大小： | 1359K |
| 代理商： | T7698 |
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Data Sheet
January 1999
T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor
80
Lucent Technologies Inc.
Frame Monitors
(continued)
Frame Monitor Status/Counter Registers
Frame Monitor Main Status Register (SR0)
This register reports on the alarm/event conditions in registers Framer_SR1—Framer_SR7. The bits in this register
are cleared on read if the clear condition is satisfied.
Table 65. Frame Monitor Main Status Register (Framer_SR0)
Facility Alarm Condition Register (Framer_SR1)
A bit set to 1 indicates the frame monitor has recently detected the corresponding alarm condition. The alarm con-
dition may or may not be present at the time of the read.
Table 66. Facility Alarm Condition Register (Framer_SR1)
Bits
0
Description
Clear Condition
A 1 indicates one of the bits in register Framer_SR1
was set. Read register SR1 for additional information.
A 1 indicates one of the bits in register Framer_SR2
was set. Read register SR2 for additional information.
A 1 indicates one of the bits in register Framer_SR3
was set. Read register SR3 for additional information.
A 1 indicates one of the bits in register Framer_SR4
was set. Read register SR4 for additional information.
A 1 indicates one of the bits in register Framer_SR5
was set. Read register SR5 for additional information.
A 1 indicates one of the bits in register Framer_SR6
was set. Read register SR6 for additional information.
A 1 indicates one of the bits in register Framer_SR7
was set. Read register SR7 for additional information.
Reserved.
When all of the bits in register
Framer_SR1 are cleared.
When all of the bits in register
Framer_SR2 are cleared.
When all of the bits in register
Framer_SR3 are cleared.
When all of the bits in register
Framer_SR4 are cleared.
When all of the bits in register
Framer_SR5 are cleared.
When all of the bits in register
Framer_SR6 are cleared.
When all of the bits in register
Framer_SR7 are cleared.
1
2
3
4
5
6
7
—
Bits
0
1
Description
Loss of Frame Alignment (LFA).
A 1 indicates the frame monitor detected a loss of frame alignment.
Loss of Superframe Alignment (LSFA).
A 1 indicates the frame monitor detected a loss of superframe
alignment in the D4 and SLC-96 framing formats. This bit is 0 in all other framing modes.
Alarm Indication Signal (AIS).
A 1 indicates the frame monitor detected an AIS pattern from its remote
line end.
Loss of Frame Alignment Since Last Read (LFALR).
A 1 indicates that the LFA state indicated in bit
0 of this register is the same LFA state from the previous read.
Lack of Time Slot 0 CRC-4 Multiframe Alignment (LTS0MFA).
A 1 indicates the frame monitor has
not detected time slot 0 CRC-4 multiframe alignment after basic frame alignment is found. This bit is 0
when receive CRC-4 checking is disabled or when the frame monitor is in the DS1 mode.
Severely Errored Frame (SEF).
A 1 indicates the frame monitor detected a severely errored frame.
Reserved.
Auxiliary Pattern Alarm (AUXP).
This bit is asserted when the frame monitor is in the LFA state and
has detected a valid CEPT AUXP This bit is 0 when the frame monitor is in the DS1 mode.
2
3
4
5
6
7
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