參數(shù)資料
型號： T7698
廠商： Lineage Power
英文描述： Quad T1/E1 Line Interface and Octal T1/E1 Monitor(四T1/E1線接口和八T1/E1監(jiān)控器)
中文描述： 四T1/E1線路接口和八路的T1/E1監(jiān)視器（四個T1/E1線接口和八T1/E1的監(jiān)控器）
文件頁數(shù)： 92/112頁
文件大?。?/td> 1359K
代理商： T7698
Data Sheet
January 1999
T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor
92
Lucent Technologies Inc.
Facility Data Links
(continued)
FDL Features
(continued)
HDLC Mode
The receive queue manager forms a status of frame (SF) byte for each HDLC frame and stores the SF byte in the
receive FDL FIFO after the last data byte of the associated frame. HDLC frames with n bytes will have (n + 1) bytes
stored in the receive FIFO. The frame check sequence (CRC) bytes of the received HDLC frame are not stored into
the receive FIFO, unless the HRPF bit (register FDL_PR0, bit 2) is set (i.e., HDLC mode with PRM is enabled).
The SF byte has the following format.
Whenever an SF byte is present in the FIFO, the end of frame (EOF) bit (register FDL_SR1, FDL bit 7) is set. The
receiver queue status (RQS) bits (register FDL_SR1, bits 0—6) report the number of bytes up to and including the
first SF byte. If no SF byte is present in the FIFO, the count directly reflects the number of data bytes available to be
read. Depending on the FDL frame size, it is possible for multiple frames to be present in the FIFO. The receive fill
level (RFL) indicator (register FDL_PR1, bits 0—5) can be programmed in the receive FDL control register to tailor
the service time interval to the system environment. The FIFO full (RF) status bit (register FDL_SR0, bit 0) is set in
the status register when the FIFO reaches the preprogrammed full position. In the HDLC mode, REOF status bit
(register FDL_SR0, bit 1) is set high when the receiver has identified the end of frame and has written the SF byte
for that frame. The FDL overrun status bit (register FDL_SR0, bit 2) is set high when the receiver needs to write
either status or data to the FIFO when the FIFO is full. An overrun condition will cause the last byte of the FIFO to
be overwritten with an SF byte indicating the overrun status. In the HDLC mode, the receive idle (RIDL) status bit
(register FDL_SR0, bit 3) is set high whenever 15 or more continuous 1s have been detected.
Transparent Mode
The receive FIFO receives FDL data from the receive frame monitor and directly loads this FDL information bit for
bit, least significant bit first. If the MATCH bit is set in the FDL control register, the receive FDL FIFO will load data
only after the matched pattern has been detected. The match character and all subsequent bytes are placed into
the receive FIFO.
Table 98. HDLC Status of Frame Byte
RSF B7
BAD CRC
RSF B6
ABORT
RSF B5
FIFO
OVERRUN
RSF B4
BAD BYTE
COUNT
RSF B3
0
RSF B2
0
RSF B1
0
RSF B0
0
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