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參數(shù)資料
| 型號： | T7698 |
| 廠商： | Lineage Power |
| 英文描述： | Quad T1/E1 Line Interface and Octal T1/E1 Monitor(四T1/E1線接口和八T1/E1監(jiān)控器) |
| 中文描述： | 四T1/E1線路接口和八路的T1/E1監(jiān)視器（四個T1/E1線接口和八T1/E1的監(jiān)控器） |
| 文件頁數(shù)： | 61/112頁 |
| 文件大?。?/td> | 1359K |
| 代理商： | T7698 |
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Data Sheet
January 1999
T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor
61
Lucent Technologies Inc.
Frame Monitors
(continued)
Frame Formats
(continued)
Representing the contents of the submultiframe check block as a polynomial, the first bit in the block, i.e., frame 0,
bit 1 or frame 8, bit 1, is taken as being the most significant bit and the least significant bit in the check block is
frame 7 or frame 15, bit 256. Similarly, C
1
is defined to be the most significant bit of the remainder and C
4
, the least
significant bit of the remainder. The encoding procedure, as described in ITU Rec. G.704, Section 2.3.3.5.2, fol-
lows:
1.
2.
3.
The CRC-4 bits in the SMF are replaced by binary 0s.
The SMF is then acted upon by the multiplication/division process referred to above.
The remainder resulting from the multiplication/division process is stored, ready for insertion into the respec-
tive CRC-4 locations of the next SMF.
The decoding procedure, as described in ITU Rec. G.704, Section 2.3.3.5.3, follows:
1.
A received SMF is acted upon by the multiplication/division process referred to above, after having its CRC-4
bits extracted and replaced by 0s.
The remainder resulting from this division process is then stored and subsequently compared on a bit-by-bit
basis with the CRC bits received in the next SMF.
If the remainder calculated in the decoder exactly corresponds to the CRC-4 bits received in the next SMF, it is
assumed that the checked SMF is error-free.
2.
3.
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