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參數(shù)資料
| 型號： | T7698 |
| 廠商： | Lineage Power |
| 英文描述： | Quad T1/E1 Line Interface and Octal T1/E1 Monitor(四T1/E1線接口和八T1/E1監(jiān)控器) |
| 中文描述： | 四T1/E1線路接口和八路的T1/E1監(jiān)視器（四個(gè)T1/E1線接口和八T1/E1的監(jiān)控器） |
| 文件頁數(shù)： | 36/112頁 |
| 文件大小： | 1359K |
| 代理商： | T7698 |
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Data Sheet
January 1999
T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor
36
Lucent Technologies Inc.
Line Interface Units: Jitter Attenuator
(continued)
Jitter Attenuator Enable
The jitter attenuator is selected using the JAR and JAT bits (register 5, bits 1 and 2) of the microprocessor interface.
These control bits are global and affect all four channels unless a given channel is in the powerdown mode
(PWRDN = 1). Because there is only one attenuator function in the device, selection must be made between either
the transmit or receive path. If both JAT and JAR are activated at the same time, the jitter attenuator will be dis-
abled.
Note that the power consumption increases slightly on a per-channel basis when the jitter attenuator is active. If jit-
ter attenuation is selected, a valid XCLK (pin 29) signal must be available.
Jitter Attenuator Receive Path Enable (JAR)
When the jitter attenuator receive bit is set (JAR = 1), the attenuator is enabled in the receive data path between
the clock/data recovery and the decoder (see Figure 4 on page 22). Under this condition, the jitter characteristics of
the jitter attenuator apply for the receiver. When JAR = 0, the clock/data recovery outputs bypass the disabled
attenuator and directly enter the decoder function. The receive path will then exhibit the jitter characteristics shown
in Figure 11 through Figure 14. If CDR = 0 (register 5, bit 0), the JAR bit is ignored because clock recovery will be
disabled.
Jitter Attenuator Transmit Path Enable (JAT)
When the jitter attenuator transmit bit is set (JAT = 1), the attenuator is enabled in the transmit data path between
the encoder and the pulse-width controller/pulse equalizer (see Figure 4 on page 22). Under this condition, the jit-
ter characteristics of the jitter attenuator apply for the transmitter. When JAT = 0, the encoder outputs bypass the
disabled attenuator and directly enter the pulse-width controller/pulse equalizer. The transmit path will then pass all
jitter from TCLK to line interface outputs TTIP/TRING.
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