參數(shù)資料
型號(hào)： T7698
廠商： Lineage Power
英文描述： Quad T1/E1 Line Interface and Octal T1/E1 Monitor(四T1/E1線接口和八T1/E1監(jiān)控器)
中文描述： 四T1/E1線路接口和八路的T1/E1監(jiān)視器（四個(gè)T1/E1線接口和八T1/E1的監(jiān)控器）
文件頁(yè)數(shù)： 7/112頁(yè)
文件大?。?/td> 1359K
代理商： T7698
Data Sheet
January 1999
T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor
7
Lucent Technologies Inc.
List of Tables
(continued)
Tables
Page
Table 107. FDL Receiver ANSI ESF Bit Codes (FDL_SR2) ..................................................................................97
Table 108. Receiver FDL FIFO Access Register (FDL_SR3) ................................................................................97
Table 109. XCLK (16x, CLKS = 0) Timing Specifications ......................................................................................98
Table 110. XCLK (1x, CLKS = 1) Timing Specifications ........................................................................................99
Table 111. Termination Components by Application ...........................................................................................100
Table 112. Absolute Maximum Ratings ...............................................................................................................101
Table 113. ESD Threshold Voltage ......................................................................................................................101
Table 114. Recommended Operating Conditions ................................................................................................101
Table 115. Power Consumption ...........................................................................................................................102
Table 116. Power Dissipation ..............................................................................................................................102
Table 117. Logic Interface Characteristics ...........................................................................................................102
Table 118. Microprocessor Interface I/O Timing Specifications ...........................................................................103
Table 119. Data Interface Timing .........................................................................................................................109
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