參數(shù)資料
型號： T7698
廠商： Lineage Power
英文描述： Quad T1/E1 Line Interface and Octal T1/E1 Monitor(四T1/E1線接口和八T1/E1監(jiān)控器)
中文描述： 四T1/E1線路接口和八路的T1/E1監(jiān)視器（四個T1/E1線接口和八T1/E1的監(jiān)控器）
文件頁數(shù)： 2/112頁
文件大?。?/td> 1359K
代理商： T7698
Data Sheet
January 1999
T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor
2
Lucent Technologies Inc.
Table of Contents
Contents
Page
Features .................................................................................................................................................................. 1
T1/E1 Line Interface Features ............................................................................................................................ 1
T1/E1 Frame Monitor Features ........................................................................................................................... 1
Facility Data Link Features ................................................................................................................................. 8
User-Programmable Microprocessor Interface ................................................................................................... 8
Applications ............................................................................................................................................................. 8
Description ............................................................................................................................................................... 8
Block Diagram ......................................................................................................................................................... 9
Pin Information ...................................................................................................................................................... 10
T7698 Device Overview ......................................................................................................................................... 15
System Interface Pin Options................................................................................................................................. 15
Microprocessor Interface ....................................................................................................................................... 16
Overview ........................................................................................................................................................... 16
Microprocessor Configuration Modes ............................................................................................................... 16
Microprocessor Interface Pinout Definitions ..................................................................................................... 17
Microprocessor Clock (MPCLK) Specifications ................................................................................................ 18
Internal Chip Select Function ........................................................................................................................... 18
Microprocessor Interface Register Architecture ............................................................................................... 19
Line Interface Units ................................................................................................................................................ 22
Line Interface Units: Receive ................................................................................................................................. 23
Data Recovery .................................................................................................................................................. 23
Jitter Accommodation and Jitter Transfer Without the Jitter Attenuator ............................................................ 23
Receiver Configuration Modes ......................................................................................................................... 23
Receive Line Interface Configuration Modes .................................................................................................... 24
DS1 Receiver Specifications ............................................................................................................................ 26
CEPT Receiver Specifications .......................................................................................................................... 28
Line Interface Units: Transmit ................................................................................................................................ 30
Output Pulse Generation .................................................................................................................................. 30
Jitter .................................................................................................................................................................. 30
Transmitter Configuration Modes ...................................................................................................................... 31
Transmitter Alarms ............................................................................................................................................ 31
DS1 Transmitter Pulse Template and Specifications ........................................................................................ 32
CEPT Transmitter Pulse Template and Specifications ...................................................................................... 33
Line Interface Units: Jitter Attenuator .................................................................................................................... 35
Generated (Intrinsic) Jitter ................................................................................................................................ 35
Jitter Transfer Function ..................................................................................................................................... 35
Jitter Accommodation ....................................................................................................................................... 35
Jitter Attenuator Enable .................................................................................................................................... 36
Line Interface Units: Loopbacks ............................................................................................................................ 39
Full Local Loopback (FLLOOP) ........................................................................................................................ 39
Remote Loopback (RLOOP) ............................................................................................................................ 39
Digital Local Loopback (DLLOOP) ................................................................................................................... 39
Line Interface Units: Other Features ..................................................................................................................... 40
Powerdown (PWRDN) ...................................................................................................................................... 40
RESET (
RESET
, SWRESET) ............................................................................................................................ 40
Loss of XCLK Reference Clock (LOXC) ........................................................................................................... 40
In-Circuit Testing and Driver High-Impedance State (ICT) ............................................................................... 40
LIU Delay Values .............................................................................................................................................. 40
Line Interface Units: Line Encoding/Decoding ....................................................................................................... 41
Alternate Mark Inversion (AMI) ......................................................................................................................... 41
T1-Binary 8 Zero Code Suppression ................................................................................................................ 41
High-Density Bipolar of Order 3 (HDB3) ........................................................................................................... 42
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