參數(shù)資料
型號： T7698
廠商： Lineage Power
英文描述： Quad T1/E1 Line Interface and Octal T1/E1 Monitor(四T1/E1線接口和八T1/E1監(jiān)控器)
中文描述： 四T1/E1線路接口和八路的T1/E1監(jiān)視器（四個T1/E1線接口和八T1/E1的監(jiān)控器）
文件頁數(shù)： 93/112頁
文件大小： 1359K
代理商： T7698
Data Sheet
January 1999
T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor
93
Lucent Technologies Inc.
Facility Data Links
(continued)
FDL Features
(continued)
Receive HDLC Operation
This section describes the standard HDLC functions performed by the T7698’s receive HDLC block. HDLC opera-
tion is the default mode of operation after the FDL receiver is enabled. The FDL receives the data link data and
clock from the frame monitor, identifies frames for proper format, reconstructs data bytes, provides bit destuffing as
necessary, and loads parallel data into the receive FIFO. HDLC frames on the serial link have the following format.
All bits between the opening flag and the CRC are considered user data bits and are stored in the FIFO buffers.
The 16 bits preceding the closing flag are the frame check sequence or cyclic redundancy check (CRC) bits.
Zero-Bit Deletion (Bit Destuffing).
The HDLC protocol recognizes three special bit patterns: flags, aborts, and
idles. These patterns have the common characteristic of containing at least six consecutive 1s. It is assumed that
zero-bit stuffing is done on user data and CRC fields of the frame to avoid mimicking one of these special patterns;
whenever five 1s occur between flags, a 0 bit is automatically inserted after the fifth 1, prior to transmission of the
next bit. When the detector detects five successive 1s followed by a 0, the 0 is assumed to have been inserted and
is deleted (bit destuffing).
Flags.
The receiver recognizes the 01111110 pattern as a flag. Two successive flags may or may not share the
intermediate 0 bit and are identified as two flags (i.e., both 011111101111110 and 0111111001111110 are recog-
nized by the T7698’s HDLC block). When another flag is identified, it is treated as the closing flag. As mentioned
above, a flag sequence in the user data or FCS fields is prevented by zero-bit insertion. The HDLC receiver recog-
nizes a single flag between frames as both a closing and opening flag.
Aborts.
When receiving a frame, the receiver recognizes the abort sequence whenever it receives a 0 followed by
seven consecutive 1s. This status results in the abort bit, and possibly the bad byte count bit and/or bad CRC bits,
being set in the status of frame status byte which is appended to the receive data queue. The last two bytes of user
data are assumed to be CRC bits and are not placed in the queue. All subsequent bytes are ignored until a valid
opening flag is received.
Idles.
In accordance with the HDLC protocol, the HDLC block recognizes 15 or more contiguous received 1s as
idle. When the HDLC block receives 15 contiguous 1s, the receiver status idle bit (RIDL) is set.
CRC.
For a given user data field, 16 additional bits that constitute an error-detecting code are added to the data
field. As defined in the HDLC protocol, the frame check sequence bits are transmitted most significant bit first and
are bit stuffed. CRC (or cyclic redundancy) is calculated as a function of the user data bits by using the ITU-T stan-
dard polynomial:
x
16
+ x
12
+ x
5
+ 1
The receiver performs the same calculation on the received bits after destuffing and compares the results to an
expected result. An error occurs if, and only if, there is a mismatch. The result of the CRC check is reported in bit 7
of the status of frame byte, which is placed in the receive FIFO after the last data byte of the frame. The CRC is not
stored in the FIFO unless the HRPF bit (register FDL_PR0, bit 2) is set.
Status of Frame Byte Description.
The receiver status is available in two ways. First, the queue manager creates
a status of frame (SF) byte for each HDLC frame and stores this status byte in the FIFO after the last data byte of
the associated frame. Thus, a frame containing n user data bytes results in n + 1 bytes present in the receive FIFO.
The SF byte has the format shown in Table 98.
Bit 7 of the SF byte is the CRC status bit. If an incorrect CRC was detected, this bit is set to 1. If the CRC was cor-
rect, the bit is 0.
Table 99. HDLC Frame Format
Opening Flag
User Data Field
Frame Check
Sequence (CRC)
16 bits
Closing Flag
01111110
≥
8 bits
01111110
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