參數(shù)資料
型號： T7698
廠商： Lineage Power
英文描述： Quad T1/E1 Line Interface and Octal T1/E1 Monitor(四T1/E1線接口和八T1/E1監(jiān)控器)
中文描述： 四T1/E1線路接口和八路的T1/E1監(jiān)視器（四個T1/E1線接口和八T1/E1的監(jiān)控器）
文件頁數(shù)： 90/112頁
文件大?。?/td> 1359K
代理商： T7698
Data Sheet
January 1999
T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor
90
Lucent Technologies Inc.
Facility Data Links
Figure 23 shows the block diagram of the receive facility data link and its interface with the receive frame monitor.
The receive frame monitor extracts the data link bits (RFD) from the DS1 or CEPT data link and generates a data
link clock (RFCK) to be used by the FDL section.
T7698 is capable of extracting the data from the facility data link in the SLC-96, DDS, ESF, and CEPT framing for-
mats. In CEPT, any one of the Sa bits (Sa4—Sa8) can be declared as the facility data link. Access to the FDL can
be through the 64-byte FIFO of the FDL block. Data passing through the FDL HDLC section may be HDLC framed
or passed through transparently.
A brief summary of the facility data link functions is given below with more details to follow in the features section.
1.
Bit-oriented message operation. The ANSI T1.403-1995 bit-oriented data link messages are recognized and
stored in register FDL_SR2. The number of times that an ANSI code must be received for detection can be
programmed from 1 to 10 by writing to register FDL_PR0, bits 4—7. When the code is detected, the RANSI bit
(register FDL_SR0, bit 4) is set.
HDLC operation. This is the default mode of operation when the FDL receiver is enabled (register FDL_PR0,
bit 1 = 1). The HDLC framer detects the HDLC flags, checks the CRC bytes, and stores the data in the receive
FIFO.
HDLC operation with performance report messages (PRM). This mode can be enabled by setting register
FDL_PR0, bits 1 and 2 high. In this case, the frame header, PRM message, and the frame check sequence are
stored in the FIFO.
Transparent operation. Setting the HTRANS bit (register FDL_PR3, bit 6) disables the HDLC processing.
Incoming data link bits are stored in the FIFO.
Transparent operation with pattern match. When the MATCH bit (register FDL_PR3, bit 5) is set high in addition
to the HTRANS bit, the facility data link starts storing the data in the FIFO only after the programmable match
character (register FDL_PR2, bits 0—7) has been detected.
2.
3.
4.
5.
5-4705(F)r.7
Figure 23. Block Diagram of the Receive Facility Data Link
RECEIVE FRAME MONITOR
RECEIVE FACILITY DATA
LINK CHARACTER
MATCH DECODER
RECEIVE FACILITY DATA LINK
HDLC FRAME MONITOR
PERFORMANCE REPORT
MESSAGE MONITOR
3-byte HEADER:
4 x 2-byte ONE-SECOND
REPORT REGISTERS
FRAME STATUS BYTE
ANSI T 1.403-1995
BIT-ORIENTED DATA LINK
MESSAGES MONITOR
ONE 8-bit REGISTER
IDENTIFYING THE ESF
BIT-ORIENTED CODE
MICROPROCESSOR INTERFACE
RECEIVE FACILITY DATA LINK
FIFO
64 8-bit LOCATIONS
RFD
RFCK
TRANSPARENT
LOSS OF FRAME
ALIGNMENT
FDL SECTION
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