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參數(shù)資料
| 型號： | T7698 |
| 廠商： | Lineage Power |
| 英文描述： | Quad T1/E1 Line Interface and Octal T1/E1 Monitor(四T1/E1線接口和八T1/E1監(jiān)控器) |
| 中文描述： | 四T1/E1線路接口和八路的T1/E1監(jiān)視器（四個T1/E1線接口和八T1/E1的監(jiān)控器） |
| 文件頁數(shù)： | 40/112頁 |
| 文件大?。?/td> | 1359K |
| 代理商： | T7698 |
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Data Sheet
January 1999
T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor
40
Lucent Technologies Inc.
Line Interface Units: Other Features
Powerdown (PWRDN)
Each line interface channel has an independent powerdown mode controlled by PWRDN (registers 6 to 9, bit 0).
This provides power savings for systems that use backup channels. If PWRDN = 1, the corresponding channel will
be in a standby mode, consuming only a small amount of power. It is recommended that the alarm registers for the
corresponding channel be masked with MASK = 1 (registers 6 to 9, bit 1) during powerdown mode. If a line inter-
face channel in powerdown mode needs to be placed into service, the channel should be turned on (PWRDN = 0)
approximately 5 ms before data is applied.
If a line interface channel will never be in service, the V
DDA
and V
DDD
pins can be connected to the ground plane,
resulting in no power consumption.
RESET (RESET, SWRESET)
The device provides both a hardware reset (
RESET
; pin 32) and a software reset (SWRESET; register 4, bit 1) that
are functionally equivalent. When the device is in reset, all signal-path and alarm monitor states are initialized to a
known starting configuration. The status registers and INT (pin 25) are also cleared. The writable microprocessor
interface registers are not affected by reset, with the exception of bits in register 4 (see the Global Control Registers
(0100, 0101) section). During a reset condition, data transmission will be interrupted.
The reset condition is initiated by setting
RESET
= 0 or SWRESET = 1 for a minimum of 10 μs. After leaving the
reset condition (with
RESET
= 1 or SWRESET = 0), the bits in register 4 will be reset and may need to be restored.
Loss of XCLK Reference Clock (LOXC)
The LOXC output (pin 31) is active when the XCLK reference clock (pin 29) is absent. The LOXC flag is asserted a
maximum of 16 μs after XCLK disappears, and deasserts immediately after detecting the first clock edge of XCLK.
During the LOXC alarm condition, the clock recovery and jitter attenuator functions are automatically disabled.
Therefore, if CDR = 1 and/or JAR = 1, the RCLK, RPD, RND, and DLOS outputs will be unknown. If CDR = 0, there
will be no effect on the receiver. If the jitter attenuator is enabled in the transmit path (JAT = 1) during this alarm
condition, then a Loss of Transmit Clock alarm, LOTC = 1, will also be indicated.
In-Circuit Testing and Driver High-Impedance State (
ICT
)
The function of the
ICT
input (pin 33) is determined by the ICTMODE bit (register 4, bit 3). If ICTMODE = 0 and
ICT
is activated (
ICT
= 0), then all output buffers (TTIP TRING, RCLK, RPD, RND, LOXC, RDY_
DTACK
, INT, AD[7:0])
are placed in a high-impedance state. For in-circuit testing, the
RESET
pin can be used to activate ICTMODE = 0
without having to write the bit. If ICTMODE = 1 and
ICT
= 0, then only the TTIP and TRING outputs of all channels
will be placed in a high-impedance state. The TTIP and TRING outputs have a limiting high-impedance capability of
approximately 8 k
.
LIU Delay Values
The transmit coder has 5 UI delay whether it is in the path or not and whether it is B8ZS or HDB3. Its delay is only
removed when in single-rail mode. The remainder of the transmit path has 4.6 UI delay. The receive decoder has
5 UI delay whether it is in the path or not and whether it is B8ZS or HDB3. Its delay is only removed when in single-
rail mode or CDR = 0. The AFE (equalizer plus slicer) delay is nearly 0 UI delay. The jitter attenuator delay is nomi-
nally 33 UI but can be 2 UI—64 UI depending on the state. The DPLL used for timing recovery has 8 UI delay.
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