參數(shù)資料
型號(hào): T7698
廠商: Lineage Power
英文描述: Quad T1/E1 Line Interface and Octal T1/E1 Monitor(四T1/E1線接口和八T1/E1監(jiān)控器)
中文描述: 四T1/E1線路接口和八路的T1/E1監(jiān)視器(四個(gè)T1/E1線接口和八T1/E1的監(jiān)控器)
文件頁數(shù): 21/112頁
文件大小: 1359K
代理商: T7698
Data Sheet
January 1999
T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor
21
Lucent Technologies Inc.
Microprocessor Interface
(continued)
Microprocessor Interface Register Architecture
(continued)
Examples of Microprocessor Writes and Reads
1.
Write 29 (hexadecimal) to register 5 of the LIU.
Step 1. Write 00 (hexadecimal) to address 1101 (this selects the LIU register bank).
Step 2. Write 29 (hexadecimal) to address 0101 (this writes 29 to the LIU register 5).
2.
Read register 2 of the LIU.
Step 1. Write 00 (hexadecimal) to address 1101 (this selects the LIU register bank).
Step 2. Read address 0010 (this reads the LIU register 2).
3.
Write 20 (hexadecimal) to register 0 of frame monitor 1.
Step 1. Write 01 (hexadecimal) to address 1101 (this selects the frame monitor 1 register bank).
Step 2. Write 20 (hexadecimal) to address 0000 (this writes 20 to the frame monitor 1 register 0).
4.
Read register 10 of frame monitor 7.
Step 1. Write 07 (hexadecimal) to address 1101 (this selects the frame monitor 7 register bank).
Step 2. Read address 1010 (this reads the frame monitor 7, register 10).
5.
Read status registers Framer_SR0—Framer_SR20 of frame monitor 5.
Step 1. Write 05 (hexadecimal) to 1101 (this selects the frame monitor 5 register bank).
Step 2. Read address 1111 (this reads the contents of register Framer_SR0).
Step 3. Read address 1111 (this reads the contents of register Framer_SR1).
Step 4. Read address 1111 (this reads the contents of register Framer _SR2).
.
Step 22. Read address 1111 (this reads the contents of register Framer_SR20).
Note that every new access to a frame monitor status register (register 15) starts the read at Framer_SR0. The
read counter is incremented internally so subsequent read commands read the contents of Framer _SR1,
Framer _SR2, etc. Also, the chip select (CS) must remain low for the entire time that register 15 is being read.
6.
Write A6 (hexadecimal) to register 0 of FDL1.
Step 1. Write 11 (hexadecimal) to address 1101 (this selects the FDL1 register bank).
Step 2. Write A6 (hexadecimal) to address 0001 (this writes A6 to FDL1 register bank).
7.
Read register 6 of FDL3.
Step 1. Write 13 (hexadecimal) to address 1101 (this selects the FDL3 register bank).
Step 2. Read address 0110 (this reads the FDL3 register 6).
8.
Read 10 bytes from the receive FIFO of FDL8.
Step 1. Write 18 (hexadecimal) to address 1101 (this selects the FDL8 register bank).
Step 2. Read address 0111 (this reads the first byte from the FDL8 FIFO).
Step 3. Read address 0111 (this reads the second byte from the FDL8 FIFO).
.
Step 11. Read address 0111 (this reads the tenth byte from the FDL8 FIFO).
Note that the FIFO pointer keeps track of the location where data has not been read.
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