參數(shù)資料
型號(hào)： T7698
廠商： Lineage Power
英文描述： Quad T1/E1 Line Interface and Octal T1/E1 Monitor(四T1/E1線接口和八T1/E1監(jiān)控器)
中文描述： 四T1/E1線路接口和八路的T1/E1監(jiān)視器（四個(gè)T1/E1線接口和八T1/E1的監(jiān)控器）
文件頁(yè)數(shù)： 56/112頁(yè)
文件大?。?/td> 1359K
代理商： T7698
Data Sheet
January 1999
T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor
56
Lucent Technologies Inc.
Frame Monitors
(continued)
Frame Formats
(continued)
T1 Frame Recovery Alignment Algorithms
When in a loss of frame alignment state, the frame monitor searches for a new frame alignment and forces its inter-
nal circuitry to this new alignment. The T7698’s synchronization circuit inhibits realignment in T1 framing formats
when repetitive data patterns emulate the T1 frame alignment patterns. The loss of frame alignment will always
force a loss of superframe alignment. T1 frame synchronization will not occur until all frame sequence emulating
patterns disappear and only one valid pattern exists. Superframe alignment is established only after frame align-
ment has been determined in the SLC-96 frame format. Table 34 gives the requirements for establishing T1 frame
and superframe alignment.
Table 34. T1 Frame Alignment Procedures
Frame Format
D4
Alignment Procedure
Using the F
T
frame position as the starting point, frame
alignment is established when 24 consecutive F
T
and F
S
frame
bits, excluding the twelfth F
S
bit (48 total frames) are received
error-free.
Using the F
T
frame position as the starting point, frame
alignment is established when 24 consecutive F
T
frame bits
(48 total frames) are received error-free. Superframe alignment
is achieved on the first valid superframe (F
S
) bit sequence
(000111000111).
Using the F
T
frame position as the starting point, frame
alignment is established when five consecutive F
T
/F
S
frame bits
and the DDS FAS in time slot 24 is received error-free. In the
DDS format, there is no search for a superframe structure.
Frame and superframe alignment is established simultaneously
using the F
E
framing bit. Alignment is established when 24
consecutive F
E
bits are received error-free.
SLC-96
DDS
ESF
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