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參數(shù)資料
| 型號： | T7698 |
| 廠商： | Lineage Power |
| 英文描述： | Quad T1/E1 Line Interface and Octal T1/E1 Monitor(四T1/E1線接口和八T1/E1監(jiān)控器) |
| 中文描述： | 四T1/E1線路接口和八路的T1/E1監(jiān)視器（四個T1/E1線接口和八T1/E1的監(jiān)控器） |
| 文件頁數(shù)： | 45/112頁 |
| 文件大?。?/td> | 1359K |
| 代理商： | T7698 |
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Data Sheet
January 1999
T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor
45
Lucent Technologies Inc.
Line Interface Units: Quad Line Interface Unit Registers
(continued)
Global Control Registers (0100, 0101)
(continued)
Channel Configuration and Control Registers (0110—1001, 1011, 1100)
The control bits in the channel configuration registers in Table 25 are used to select equalization, loopbacks,
AIS generation, channel alarm masking, and the channel powerdown mode for each channel (1—4). The
PWRDN[1—4], MASK[1—4], and XAIS[1—4] bits are active-high. These are read/write registers.
Control bits for zero substitution coding for channels 1—4 are listed in Table 27 and Table 26.
* A numerical suffix identifies the channel number.
Channel suffix not shown in the description.
Table 24. Global Control Register (0101)
Bits
Symbol
Description
Global Control Register (5)
The CDR bit is used to enable and disable the clock/data recovery function.
The JAR is used to enable and disable the jitter attenuator function in the
receive path. The JAR and JAT control bits are mutually exclusive; i.e., either
JAR or the JAT control bit can be set, but not both.
The JAT is used to enable and disable the jitter attenuator function in the trans-
mit path. The JAT and JAR control bits are mutually exclusive; i.e., either JAT or
the JAR control bit should be set, but not both.
The CODE bit is used to enable the B8ZS/HDB3 zero substitution coding. It is
used in conjunction with the DUAL bit and is valid only for single-rail operation.
The DUAL bit is used to select single or dual-rail mode of operation.
The ALM bit selects the transmit and receive data polarity (i.e., active-low or
active-high). The ALM and ACM bits are used together to determine the trans-
mit and receive data retiming modes.
The ACM bit selects the positive or negative edge of the receive clock
(RCLK[4:1]) for receive data retiming. The ACM and ALM bits are used
together to determine the transmit and receive data retiming modes.
The LOSSD bit selects the shutdown function for the digital loss of signal alarm
(DLOS).
0
1
CDR
JAR
2
JAT
3
CODE
4
5
DUAL
ALM
6
ACM
7
LOSSD
Table 25. Channel Configuration Registers (0110—1001)
Bits
Symbol
*
Description
Channel Configuration Registers
(6—9)
The PWRDN bit powers down a channel when not used.
The MASK bit masks all interrupts for the channel.
The XAIS bit enables transmission of an all-1s signal to the line interface.
The LOOPB and LOOPA bits select the channel loopback modes.
0
1
2
3
PWRDN[4:1]
MASK[4:1]
XAIS[4:1]
LOOPB[4:1]
4
5
LOOPA[4:1]
EQC[4:1],
6
7
EQB[4:1],
EQA[4:1]
The EQC, EQB, and EQA bits select the type of service (DS1 or CEPT)
and the associated transmitter cable equalization/termination imped-
ances.
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