- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383876 > T7698 (Lineage Power) Quad T1/E1 Line Interface and Octal T1/E1 Monitor(四T1/E1線接口和八T1/E1監(jiān)控器) PDF資料下載
參數(shù)資料
| 型號： | T7698 |
| 廠商： | Lineage Power |
| 英文描述： | Quad T1/E1 Line Interface and Octal T1/E1 Monitor(四T1/E1線接口和八T1/E1監(jiān)控器) |
| 中文描述： | 四T1/E1線路接口和八路的T1/E1監(jiān)視器（四個T1/E1線接口和八T1/E1的監(jiān)控器） |
| 文件頁數(shù)： | 8/112頁 |
| 文件大?。?/td> | 1359K |
| 代理商： | T7698 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁
Data Sheet
January 1999
T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor
8
Lucent Technologies Inc.
Features
(continued)
T1/E1 Frame Monitor Features
(continued)
I
Alarm reporting, performance monitoring, and main-
tenance
— Status registers for detection of red alarm, remote
frame alarm, and alarm indication signal
conditions, errors, and violations
— 16-bit counter registers for counting:
1. Line format violations (bipolar, coding,
excessive zeros)
2. Framing bit errors
3. CRC errors
4. CEPT E bit = 0 conditions
5. CEPT Sa6 codes
6. Errored seconds
7. Bursty errored seconds
8. Severely errored seconds
9. Unavailable seconds
— Selectable errored event monitoring for errored
and severely errored seconds processing with
optional programmable thresholds for errored
seconds, bursty errored seconds, and severely
errored seconds
I
Compatible with the receive section of Lucent’s
T7630
Facility Data Link Features
I
HDLC or transparent mode
I
64-byte receive FIFO capable of holding multiple
frames
I
Detection of the ANSI ESF bit-oriented messages
I
Monitoring of the ANSI performance report mes-
sages
User-Programmable Microprocessor Inter-
face
I
16 MHz read and write access with no wait-states
I
4-bit address, 8-bit data interface
I
Programmable Intel*or Motorola
interface modes
I
Demultiplexed or multiplexed address and data bus
Applications
I
T1/E1 network performance monitoring
I
SONET/SDH multiplexers
I
Asynchronous multiplexers (M13)
I
Digital access cross connects (DACs)
I
Channel banks
I
Digital radio base stations, remote wireless modules
I
PBX interfaces
Description
The T7698 is an integrated quad line interface contain-
ing four line transmit and receive channels and an octal
frame monitor for use in both North American (T1/DS1)
and European (E1/CEPT) applications. The line inter-
face unit has the same functions as the Lucent T7690,
and the frame monitors are compatible with the receive
section of the Lucent T7630. Included is a parallel
microprocessor interface that allows the user to define
the architecture, initiate loopbacks, and monitor alarms.
The interface is compatible with many commercially
available microprocessors. The functional block dia-
gram of the T7698 is shown in Figure 1.
The block diagram of the line interface unit is shown in
Figure 4. The line receiver performs clock and data
recovery using a fully integrated digital phase-locked
loop. This digital implementation prevents false lock
conditions that are common when recovering sparse
data patterns with analog phase-locked loops. Equal-
ization circuitry in the receiver guarantees a high level
of interference immunity. As an option, the raw sliced
data (no retiming) can be output on the receive data
pins. Transmit equalization is implemented with low-
impedance output drivers that provide shaped wave-
forms to the transformer, guaranteeing template con-
formance. The quad device will interface to the digital
cross connect (DSX) at lengths of up to 655 ft. for DS1
operation or to line impedances of 75
or 120
for
CEPT operation.
A selectable jitter attenuator may be placed in the
receive signal path for low-bandwidth line-synchronous
applications, or it may be placed in the transmit path for
multiplexer applications where DS1/CEPT signals are
demultiplexed from higher rate signals. The jitter atten-
uator will perform the clock smoothing required on the
resulting demultiplexed gapped clock.
* Intelis a registered trademark of Intel Corporation.
Motorola s a registered trademark of Motorola, Inc.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| T7705A | SUPPLY-VOLTAGE SUPERVISORS |
| T8100A | H.100/H.110 Interface and Time-Slot Interchanger(H.100/H.110接口和干線時間段交換機) |
| T8100 | H.100/H.110 Interface and Time-Slot Interchanger(H.100/H.110接口和干線時隙交換機) |
| T8102 | H.100/H.110 Interface and Time-Slot Interchanger(H.100/H.110接口和干線時隙交換機) |
| T8105 | H.100/H.110 Interface and Time-Slot Interchanger(H.100/H.110接口和干線時隙交換機) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T77 | 制造商:Thomas & Betts 功能描述:2-1/2"CONDUIT BODY,IRON,T,F-7 制造商:Cooper Crouse-Hinds 功能描述: 制造商:Thomas & Betts 功能描述:Fittings T-Fitting 2.5inch Non-Thread Iron |
| T7700 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Core2 Duo Processors and Core2 Extreme Processors for Platforms Based on Mobile 965 Express Chipset Family |
| T77000150 | 制造商:Assembly Value Added 功能描述: |
| T7705102CA | 制造商:Texas Instruments 功能描述: |
| T7705A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SUPPLY-VOLTAGE SUPERVISORS |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。