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參數資料
| 型號： | T7698 |
| 廠商： | Lineage Power |
| 英文描述： | Quad T1/E1 Line Interface and Octal T1/E1 Monitor(四T1/E1線接口和八T1/E1監(jiān)控器) |
| 中文描述： | 四T1/E1線路接口和八路的T1/E1監(jiān)視器（四個T1/E1線接口和八T1/E1的監(jiān)控器） |
| 文件頁數： | 96/112頁 |
| 文件大?。?/td> | 1359K |
| 代理商： | T7698 |
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Data Sheet
January 1999
T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor
96
Lucent Technologies Inc.
Facility Data Links
(continued)
Facility Data Link Parameter/Status Registers
(continued)
Table 102. FDL Receiver Fill Level Control Register (FDL_PR1)
Table 103. FDL Receiver Match Character Register (FDL_PR2)
Table 104. FDL Transparent Mode Control Register (FDL_PR3)
Bits
0—5
Description
Receive Fill Level (RFL[0:5]).
Bits 0—5 define the receive FIFO full threshold value that will cause the
receive FIFO fill (RF) status bit to be set. RFL = 00000 forces the receive FIFO to set the RF bit when the
receive FIFO is completely full. RFL = 01111 will force the receive FIFO to set the RF bit when the receive
FIFO contains 15 or more bytes.
Reserved.
6—7
Bits
0—7
Description
Receiver Match Character (RHMC0—RHMC7).
This character is used only in the transparent mode
(register FDL_PR3, bit 6 = 1). When the pattern match bit (register FDL_PR3, bit 5) is set to 1, the
receiver searches the incoming bit stream for the receiver match character. Data is loaded into the receive
FIFO only after this character has been identified. The byte identified as matching the receiver match
character is the first byte loaded into the FIFO. The default is to search for an HDLC flag, but any charac-
ter can be programmed by the user. The search for the receive match character is in a sliding window
fashion.
Bits
0—2
3
Description
Reserved.
Match Status (MSTAT).
Read only. When this bit is set to 1, the receiver match character has been rec-
ognized. If no match is being performed (register FDL_PR3, bit 5 = 0), the MSTAT bit is set to 1 automat-
ically when the first bit is received.
Reserved.
Should be set to 0.
Pattern Match (MATCH).
When this bit is set to 1, the FDL receiver does not load the data into the
receive FIFO until the receive match character has been detected. When this bit is 0, the receiver loads
the data into the receive FIFO without searching for a match character.
FDL Transparent Mode (HTRANS).
When this bit is set to 1, the FDL receiver performs no HDLC pro-
cessing on incoming data.
FDL Test.
This bit is reserved for manufacturing test purposes only and should be set to 0.
4
5
6
7
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