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參數(shù)資料
| 型號： | T7698 |
| 廠商： | Lineage Power |
| 英文描述： | Quad T1/E1 Line Interface and Octal T1/E1 Monitor(四T1/E1線接口和八T1/E1監(jiān)控器) |
| 中文描述： | 四T1/E1線路接口和八路的T1/E1監(jiān)視器（四個(gè)T1/E1線接口和八T1/E1的監(jiān)控器） |
| 文件頁數(shù)： | 23/112頁 |
| 文件大?。?/td> | 1359K |
| 代理商： | T7698 |
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Data Sheet
January 1999
T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor
23
Lucent Technologies Inc.
Line Interface Units: Receive
Data Recovery
The receive line interface unit (RLIU) format is bipolar
alternate mark inversion (AMI). The data rate tolerance
is ±130 ppm (DS1) or ±80 ppm (CEPT). The receiver
first restores the incoming data and detects analog loss
of signal. Subsequent processing is optional and
depends on the programmable device configuration
established within the microprocessor interface regis-
ters. The RLIU utilizes an equalizer to operate on line
length with up to 15 dB of loss at 772 kHz (DS1) or
13 dB loss at 1.024 MHz (CEPT). The signal is then
peak-detected and sliced to produce digital representa-
tions of the data.
Selectable clock and data recovery, digital loss of sig-
nal, jitter attenuation, and data decoding are per-
formed. For applications bypassing the clock and data
recovery function (CDR = 0), the receive digital output
format is unretimed sliced data (RZ positive and nega-
tive data). For clock and data recovery applications
(CDR = 1), the receive digital output format is nonre-
turn to zero (NRZ) with selectable dual-rail or single-rail
system interface. The recovered clock (RCLK, pins 15,
37, 65, 87) is only provided when CDR = 1 (see Table 2
above).
The clock is recovered by a digital phase-locked loop
that uses XCLK (pin 29) as a reference to lock to the
data rate component. Because the internal reference
clock is a multiple of the received data rate, the RCLK
output (pins 15, 37, 65, 87) will always be a valid DS1/
CEPT clock that eliminates false-lock conditions. Dur-
ing periods with no receive input signal, the free-run
frequency of RCLK is defined to be either XCLK/16 or
XCLK, depending on the state of CLKS (pin 1). RCLK
is always active with a duty-cycle centered at 50%,
deviating by no more than ±5%. Valid data is recovered
within the first few bit periods after the application of
XCLK. The delay of the data through the receive cir-
cuitry is approximately 1 to 14 bit periods, depending
on the CDR and CODE configurations. Additional delay
is introduced if the jitter attenuator is selected for oper-
ation in the receive path (see the LIU Delay Values sec-
tion, page 40).
Jitter Accommodation and Jitter Transfer
Without the Jitter Attenuator
The RLIU is designed to accommodate large amounts
of input jitter. The RLIU’s jitter performance exceeds
the requirements shown in the RLIU Specifications
tables (Table 10 and Table 11). Typical receiver perfor-
mance without the jitter attenuator in the path is shown
in Figure 5 through Figure 8. Jitter transfer is indepen-
dent of input ones density on the line interface.
Receiver Configuration Modes
Clock/Data Recovery Mode (CDR)
The clock/data recovery function in the receive path is
selectable via the CDR bit (register 5, bit 0). If CDR = 1,
the clock and data recovery function is enabled and
provides a recovered clock (RCLK) with retimed data
(RPD/RDATA, RND). If CDR = 0, the clock and data
recovery function is disabled, and the RZ data from the
slicers is provided over RPD and RND to the system. In
this mode, ALOS is available on the RCLK/ALOS pins,
and downstream functions selected by microprocessor
register 5 (JAR, ACM, LOSSD) are ignored.
Zero Substitution Decoding (CODE)
When single-rail operation is selected with DUAL = 0
(register 5, bit 4), the B8ZS/HDB3 decoding can be
selected. CODE = 1 selects the B8ZS/HDB3 decoding
operation in all four channels, regardless of the state of
the CODE[1—4] bits. The B8ZS/HDB3 decoding oper-
ation can be selected for individual channels indepen-
dently by setting CODE = 0 and programming
CODE[1—4] bits for the respective channels.
Note:
Encoding and decoding are not independent.
Selecting B8ZS/HDB3 decoding in the receiver
selects B8ZS/HDB3 encoding in the transmitter.
Table 7. Register Map for CODE Bits
Name
Location
Register
5
12
12
11
11
Bit
3
7
6
6
4
CODE
CODE1
CODE2
CODE3
CODE4
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