參數(shù)資料
型號： T7698
廠商： Lineage Power
英文描述： Quad T1/E1 Line Interface and Octal T1/E1 Monitor(四T1/E1線接口和八T1/E1監(jiān)控器)
中文描述： 四T1/E1線路接口和八路的T1/E1監(jiān)視器（四個T1/E1線接口和八T1/E1的監(jiān)控器）
文件頁數(shù)： 6/112頁
文件大小： 1359K
代理商： T7698
Data Sheet
January 1999
T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor
6
Lucent Technologies Inc.
List of Tables
(continued)
Tables
Page
Table 54. ET1 Errored Event Enable Register (Framer_PR4) .............................................................................. 76
Table 55. ET1 Remote End Errored Event Enable Register (Framer_PR5) ......................................................... 76
Table 56. NT1 Errored Event Enable Register (Framer_PR6) .............................................................................. 76
Table 57. NT1 Remote End Errored Event Enable Register (Framer_PR7) ......................................................... 76
Table 58. Errored Second Threshold Register (Framer_PR8) .............................................................................. 77
Table 59. SES Threshold Register (Framer_PR9—Framer_PR10) ...................................................................... 77
Table 60. BES Threshold Register (Framer_PR11) .............................................................................................. 77
Table 61. Frame Monitor Exercise Register (Framer_PR12) ................................................................................ 77
Table 62. Frame Monitor Exercise Register (Framer_PR12) Bits 5—0 ................................................................ 78
Table 63. Frame Monitor CRC Option Register (Framer_PR14) .......................................................................... 79
Table 64. Frame Monitor Status/Counter Register (Framer_SR) .......................................................................... 79
Table 65. Frame Monitor Main Status Register (Framer_SR0) ............................................................................. 80
Table 66. Facility Alarm Condition Register (Framer_SR1) .................................................................................. 80
Table 67. Facility Remote Alarm Status Register (Framer_SR2) .......................................................................... 81
Table 68. Local and Remote ET Facility Event Register (Framer_SR3) ............................................................... 82
Table 69. Local and Remote Network Termination-1 Facility Event Register (Framer_SR4) ............................... 83
Table 70. Facility Event Register (Framer_SR5) ................................................................................................... 84
Table 71. Facility Errored Event Register (Framer_SR6) ...................................................................................... 84
Table 72. Facility Out of Unavailable State Register (Framer_SR7) ..................................................................... 85
Table 73. Bipolar Violation Counter Registers (Framer_SR8—Framer_SR9) ...................................................... 85
Table 74. Framing Bit Error Counter Registers (Framer_SR10—Framer_SR11) ................................................. 85
Table 75. CRC-4 Error Counter Register (Framer_SR12—Framer_SR13) .......................................................... 86
Table 76. E-Bit Counter Register (Framer_SR14—Framer_SR15) ...................................................................... 86
Table 77. CRC-4 Errors at NT1 from NT2 Counter Registers (Framer_SR16—Framer_SR17) ........................... 86
Table 78. E Bit at NT1 from NT2 Counter Registers (Framer_SR18—Framer_SR19) ......................................... 86
Table 79. ET Errored Seconds Counter Register (Framer_SR20—Framer_SR21) .............................................. 87
Table 80. ET Bursty Errored Seconds Counter Register (Framer_SR22—Framer_SR23) .................................. 87
Table 81. ET Severely Errored Seconds Counter Register (Framer_SR24—Framer_SR25) ............................... 87
Table 82. ET Unavailable Seconds Counter Register (Framer_SR26—Framer_SR27) ....................................... 87
Table 83. ET-RE Errored Seconds Counter Register (Framer_SR28—Framer_SR29) ....................................... 87
Table 84. ET-RE Bursty Errored Seconds Counter Register (Framer_SR30—Framer_SR31) ............................ 87
Table 85. ET-RE Severely Errored Seconds Counter Register (Framer_SR32—Framer_SR33) ........................ 88
Table 86. ET-RE Unavailable Seconds Counter Register (Framer_SR34—Framer_SR35) ................................. 88
Table 87. NT1 Errored Seconds Counter Register (Framer_SR36—Framer_SR37) ........................................... 88
Table 88. NT1 Bursty Errored Seconds Counter Register (Framer_SR38—Framer_SR39) ................................ 88
Table 89. NT1 Severely Errored Seconds Counter Register (Framer_SR40—Framer_SR41) ............................ 88
Table 90. NT1 Unavailable Seconds Counter Register (Framer_SR42—Framer_SR43) ..................................... 88
Table 91. NT1-RE Errored Seconds Counter Register (Framer_SR44—Framer_SR45) ..................................... 89
Table 92. NT1-RE Bursty Errored Seconds Counter Register (Framer_SR46—Framer_SR47) .......................... 89
Table 93. NT1-RE Severely Errored Seconds Counter Register (Framer_SR48—Framer_SR49) ...................... 89
Table 94. NT1-RE Unavailable Seconds Counter Register (Framer_SR50—Framer_SR51) .............................. 89
Table 95. Received NOT FAS TSO RSA and E Bits Framer_(SR52) ................................................................... 89
Table 96. FDL ANSI Bit Code Status Register (FDL_SR2) ................................................................................... 91
Table 97. Performance Report Message Structure ............................................................................................... 91
Table 98. HDLC Status of Frame Byte .................................................................................................................. 92
Table 99. HDLC Frame Format ............................................................................................................................. 93
Table 100. Facility Data Link Registers ................................................................................................................. 95
Table 101. FDL Configuration Control Register (FDL_PR0) ................................................................................. 95
Table 102. FDL Receiver Fill Level Control Register (FDL_PR1) ......................................................................... 96
Table 103. FDL Receiver Match Character Register (FDL_PR2) ......................................................................... 96
Table 104. FDL Transparent Mode Control Register (FDL_PR3) ......................................................................... 96
Table 105. FDL Fill Status Register (FDL_SR0) ................................................................................................... 97
Table 106. FDL Receiver Status Register (FDL_SR1) .......................................................................................... 97
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