參數(shù)資料
型號(hào)： T7698
廠商： Lineage Power
英文描述： Quad T1/E1 Line Interface and Octal T1/E1 Monitor(四T1/E1線接口和八T1/E1監(jiān)控器)
中文描述： 四T1/E1線路接口和八路的T1/E1監(jiān)視器（四個(gè)T1/E1線接口和八T1/E1的監(jiān)控器）
文件頁(yè)數(shù)： 87/112頁(yè)
文件大?。?/td> 1359K
代理商： T7698
Data Sheet
January 1999
T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor
87
Lucent Technologies Inc.
Frame Monitors
(continued)
Frame Monitor Status/Counter Registers
(continued)
The following registers are dedicated to the exchange termination and its remote end interface. The alarm condi-
tions to evaluate errored seconds and severely errored seconds are defined in the ET1 and ET1-remote enable
registers (registers Framer_PR4 and Framer_PR5). The ET errored seconds and severely errored seconds
counters monitor the occurrences of CRC errors or receive framing bit errors. The ET-RE errored seconds and
severely errored seconds counters monitor the occurrences of received E bits = 0.
Table 79. ET Errored Seconds Counter Register (Framer_SR20—Framer_SR21)
Table 80. ET Bursty Errored Seconds Counter Register (Framer_SR22—Framer_SR23)
Table 81. ET Severely Errored Seconds Counter Register (Framer_SR24—Framer_SR25)
Table 82. ET Unavailable Seconds Counter Register (Framer_SR26—Framer_SR27)
Table 83. ET-RE Errored Seconds Counter Register (Framer_SR28—Framer_SR29)
Table 84. ET-RE Bursty Errored Seconds Counter Register (Framer_SR30—Framer_SR31)
Byte
MSB
LSB
Bits
7—0
7—0
Description
ET errored seconds counter (bit 15—bit 8).
ET errored seconds counter (bit 7—bit 0).
Byte
MSB
LSB
Bits
7—0
7—0
Description
ET bursty errored seconds counter (bit 15—bit 8).
ET bursty errored seconds counter (bit 7—bit 0).
Byte
MSB
LSB
Bits
7—0
7—0
Description
ET severely errored seconds counter (bit 15—bit 8).
ET severely errored seconds counter (bit 7—bit 0).
Byte
MSB
LSB
Bits
7—0
7—0
Description
ET unavailable seconds counter bits (bit 15—bit 8).
ET unavailable seconds counter bits (bit 7—bit 0).
Byte
MSB
LSB
Bits
7—0
7—0
Description
ET-RE errored seconds counter (bit 15—bit 8).
ET-RE errored seconds counter (bit 7—bit 0).
Byte
MSB
LSB
Bits
7—0
7—0
Description
ET-RE bursty errored seconds counter (bit 15—bit 8).
ET-RE bursty errored seconds counter (bit 7—bit 0).
相關(guān)PDF資料
PDF描述
T7705A SUPPLY-VOLTAGE SUPERVISORS
T8100A H.100/H.110 Interface and Time-Slot Interchanger(H.100/H.110接口和干線時(shí)間段交換機(jī))
T8100 H.100/H.110 Interface and Time-Slot Interchanger(H.100/H.110接口和干線時(shí)隙交換機(jī))
T8102 H.100/H.110 Interface and Time-Slot Interchanger(H.100/H.110接口和干線時(shí)隙交換機(jī))
T8105 H.100/H.110 Interface and Time-Slot Interchanger(H.100/H.110接口和干線時(shí)隙交換機(jī))
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
T77 制造商:Thomas & Betts 功能描述:2-1/2"CONDUIT BODY,IRON,T,F-7 制造商:Cooper Crouse-Hinds 功能描述: 制造商:Thomas & Betts 功能描述:Fittings T-Fitting 2.5inch Non-Thread Iron
T7700 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Core2 Duo Processors and Core2 Extreme Processors for Platforms Based on Mobile 965 Express Chipset Family
T77000150 制造商:Assembly Value Added 功能描述:
T7705102CA 制造商:Texas Instruments 功能描述:
T7705A 制造商:TI 制造商全稱:Texas Instruments 功能描述:SUPPLY-VOLTAGE SUPERVISORS
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*