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參數(shù)資料
| 型號： | T7698 |
| 廠商： | Lineage Power |
| 英文描述： | Quad T1/E1 Line Interface and Octal T1/E1 Monitor(四T1/E1線接口和八T1/E1監(jiān)控器) |
| 中文描述： | 四T1/E1線路接口和八路的T1/E1監(jiān)視器（四個T1/E1線接口和八T1/E1的監(jiān)控器） |
| 文件頁數(shù)： | 79/112頁 |
| 文件大小： | 1359K |
| 代理商： | T7698 |
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Data Sheet
January 1999
T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor
79
Lucent Technologies Inc.
Frame Monitors
(continued)
Frame Monitor Parameter/Control Registers
(continued)
Table 62. Frame Monitor Exercise Register (Framer_PR12) Bits 5—0
(continued)
Frame Monitor CRC Option Register (Framer_PR14)
These bits enable/disable various CRC control options.
Table 63. Frame Monitor CRC Option Register (Framer_PR14)
Frame Monitor Status/Counter Register (Framer_SR)
Frame monitor status/counter register (register 15) is a read-only register and provides access to the status and
counter registers Framer_SR0—Framer_SR52. Every new access to this register starts the read at register
Framer_SR0. To read status registers Framer_SR1 to Framer_SR52, the first read must be followed by subsequent
reads. The read address is incremented internally, so subsequent reads will access registers Framer_SR1—
Framer_SR52. The chip select (CS) must remain low for the entire time that register 15 is being read.
Table 64. Frame Monitor Status/Counter Register (Framer_SR)
Exercise Type
5
4
3
2
1
0
Exercise
Framing
Format
All
Status Counters
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
CRC error counter
Bursty errored second counter
Errored second counter
Severely errored second counter
Unavailable second counter
Line format violation counter
Frame-bit error counter
Factory test
Reserved
Manufacturer’s
All
All
All other combinations
Bit
0
Description
A 0 forces loss of frame alignment due to excessive CRC errors for
the ESF and CEPT with CRC-4 modes. Setting this bit to 1 prevents
CRC errors from forcing loss of frame alignment.
This bit applies to ESF mode only. If bit 0 above is 0 (i.e., LFA due to
CRC errors is enabled), then setting this bit to 0 forces LFA due to
32 CRC-6 errors out of 33 CRC checks, and setting this bit to 1
forces LFA due to greater than 320 CRC-6 errors in one second.
Reserved.
1
2—7
Bit
0—7
Description
Status registers Framer_SR0—Framer_SR52 are read through this register.
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