參數(shù)資料
型號: T7698
廠商: Lineage Power
英文描述: Quad T1/E1 Line Interface and Octal T1/E1 Monitor(四T1/E1線接口和八T1/E1監(jiān)控器)
中文描述: 四T1/E1線路接口和八路的T1/E1監(jiān)視器(四個T1/E1線接口和八T1/E1的監(jiān)控器)
文件頁數(shù): 4/112頁
文件大小: 1359K
代理商: T7698
Data Sheet
January 1999
T7698 Quad T1/E1 Line Interface and Octal T1/E1 Monitor
4
Lucent Technologies Inc.
List of Figures
Figures
Page
Figure 1. T7698 Block Diagram ................................................................................................................................9
Figure 2. T7698 Pin Diagram .................................................................................................................................10
Figure 3. T7698’s Secondary Register Bank Architecture ......................................................................................20
Figure 4. Block Diagram of the Quad Line Interface Unit (Single Channel) ...........................................................22
Figure 5. DS1/T1 Receiver Jitter Accommodation Without Jitter Attenuator ..........................................................27
Figure 6. DS1/T1 Receiver Jitter Transfer Without Jitter Attenuator ......................................................................27
Figure 7. CEPT/E1 Receiver Jitter Accommodation Without Jitter Attenuator .......................................................29
Figure 8. CEPT/E1 Receiver Jitter Transfer Without Jitter Attenuator ...................................................................29
Figure 9. DSX-1 Isolated Pulse Template ..............................................................................................................32
Figure 10. ITU-T G.703 Pulse Template ................................................................................................................33
Figure 11. DS1/T1 Receiver Jitter Accommodation with Jitter Attenuator ..............................................................37
Figure 12. DS1/T1 Jitter Transfer of the Jitter Attenuator .......................................................................................37
Figure 13. CEPT/E1 Receiver Jitter Accommodation with Jitter Attenuator ...........................................................38
Figure 14. CEPT/E1 Jitter Transfer of the Jitter Attenuator ....................................................................................38
Figure 15. Block Diagram of the Receive Frame Monitor Section ..........................................................................48
Figure 16. Block Diagram of the Octal Receive Frame Monitor .............................................................................49
Figure 17. Block Diagram of the Frame Monitor .....................................................................................................50
Figure 18. T1 Frame Structure ...............................................................................................................................51
Figure 19. ITU 2.048 Mbits/s Basic Frame and CRC-4 Multiframe Structures .......................................................57
Figure 20. T7698 Receive CRC-4 Multiframe Search Algorithm Using the 100 ms Internal Timer ........................63
Figure 21. CEPT Loss of CRC-4 Multiframe Alignment Recovery Algorithms: T7698 Receive CRC-4 Multiframe
Search Algorithm for Automatic, CRC-4/Non-CRC-4 Equipment Interworking as Defined by ITU
(from ITU Rec. G.706, Annex B.2.2 - 1991) ..........................................................................................65
Figure 22. The T and V Reference Points for a Typical CEPT E1 Application .......................................................69
Figure 23. Block Diagram of the Receive Facility Data Link ...................................................................................90
Figure 24. Line Termination Circuitry ...................................................................................................................100
Figure 25. Mode 1—Read Cycle Timing (MPMODE = 0, MPMUX = 0 ) ..............................................................105
Figure 26. Mode 1—Write Cycle Timing (MPMODE = 0, MPMUX = 0) ...............................................................105
Figure 27. Mode 2—Read Cycle Timing (MPMODE = 0, MPMUX = 1) ...............................................................106
Figure 28. Mode 2—Write Cycle Timing (MPMODE = 0, MPMUX = 1) ...............................................................106
Figure 29. Mode 3—Read Cycle Timing (MPMODE = 1, MPMUX = 0) ...............................................................107
Figure 30. Mode 3—Write Cycle Timing (MPMODE = 1, MPMUX = 0) ...............................................................107
Figure 31. Mode 4—Read Cycle Timing (MPMODE = 1, MPMUX = 1) ...............................................................108
Figure 32. Mode 4—Write Cycle Timing (MPMODE = 1, MPMUX = 1) ...............................................................108
Figure 33. Interface Data Timing (ACM = 0) ........................................................................................................109
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