參數(shù)資料
型號： OR4E02-2BM680I
英文描述： FPGA
中文描述： FPGA的
文件頁數(shù)： 78/153頁
文件大?。?/td> 2737K
代理商： OR4E02-2BM680I
78
Lattice Semiconductor
Data Sheet
November, 2002
ORCA
Series 4 FPGAs
Timing
Characteristics
To
define
speed
grades,
the
ORCA
series
part
number
designation
(see
Ordering
Information)
uses
a
single-digit
number
to
designate
a
speed
grade.
This
number
is
not
related
to
any
single
ac
parameter.
Higher
numbers
indi-
cate
a
faster
set
of
timing
parameters.
The
actual
speed
sorting
is
based
on
testing
the
delay
in
a
path
consisting
of
an
input
buffer,
combinatorial
delay
through
all
PLCs
in
a
row,
and
an
output
buffer.
Other
tests
are
then
done
to
verify
other
delay
parameters,
such
as
routing
delays,
setup
times
to
FFs,
etc.
The
most
accurate
timing
characteristics
are
reported
by
the
timing
analyzer
in
ispLEVER
design
software.
A
timing
report
provided
by
the
development
system
after
layout
divides
path
delays
into
logic
and
routing
delays.
The
timing
analyzer
can
also
provide
logic
delays
prior
to
layout.
While
this
allows
routing
budget
estimates,
there
is
wide
variance
in
routing
delays
associated
with
different
layouts.
The
logic
timing
parameters
noted
in
the
Electrical
Characteristics
section
of
this
data
sheet
are
the
same
as
those
in
ispLEVER.
In
the
timing
tables
that
follow,
symbol
names
are
generally
a
concatenation
of
the
PFU
operating
mode
(as
defined
in
Table
3)
and
the
parameter
type.
The
setup,
hold,
and
propagation
delay
parameters,
defined
below,
are
designated
in
the
symbol
name
by
the
SET,
HLD,
and
DEL
characters,
respectively.
The
values
given
for
the
parameters
are
the
same
as
those
used
during
production
testing
and
speed
binning
of
the
devices.
The
junction
temperature
and
supply
voltage
used
to
characterize
the
devices
are
listed
in
the
delay
tables
and
the
delay
values
in
this
data
sheet
are
from
ispLEVER.
Actual
delays
at
nominal
temperature
and
voltage
for
best-case
processes
can
be
much
better
than
the
values
given.
It
should
be
noted
that
the
junction
temperature
used
in
the
tables
is
generally
85
°C
or
100
°C,
based
on
the
tem-
perature
grade
of
the
device.
The
junction
temperature
for
the
FPGA
depends
on
the
power
dissipated
by
the
device,
the
package
thermal
characteristics
(
Θ
JA
),
and
the
ambient
temperature,
as
calculated
in
the
following
equation
and
as
discussed
further
in
the
Package
Thermal
Characteristics
section:
T
Jmax
=
T
Amax
+
(P
Θ
JA
)
°C
Note
: The
user
must
determine
this
junction
temperature
to
see
if
the
delays
from
ispLEVER
should
be
derated
based
on
the
following
derating
tables.
Table
37—Table
38
provide
approximate
power
supply
and
junction
temperature
derating
for
Series
4
commercial
and
industrial
devices.
The
delay
values
in
this
data
sheet
and
reported
by
ispLEVER
are
shown
as
1.00
in
the
tables.
The
method
for
determining
the
maximum
junction
temperature
is
defined
in
the
Package
Thermal
Charac-
teristics
section.
Taken
cumulatively,
the
range
of
parameter
values
for
best-case
vs.
worst-case
processing,
sup-
ply
voltage,
and
junction
temperature
can
approach
3
to
1.
The
typical
timing
path
in
Series
4
is
made
up
of
both
3.3
V
(V
DD
IO
and/or
V
DD
33)
components
and
1.5
V
(V
DD
15)
components.
For
example,
all
I/O
circuits
use
V
DD
IO
at
the
device
interface
but
all
internal
routing
and
I/O
register
logic
use
V
DD
15.
Thus
actual
voltage
derating
needs
to
be
done
based
on
multiple
parameters.
A
simple
approxi-
mation
is
that
50%
of
the
delay
path
is
due
to
each
of
these
parameters.
All
internal
paths
use
V
DD
15
for
logic
and
V
DD
33
for
routing,
but
if
V
DD
33
remains
above
3.0
V
the
internal
delays
can
be
assumed
to
be
dependent
on
V
DD
15
derating
values
only.
Note
however
that
temperature
derating
is
approximately
the
same
percentage
for
all
three
supply
voltages
thus
allowing
one
temperature
derating
value
to
be
used.
For
the
most
accurate
results,
volt-
age
and
temperature
derating
capabilities
to
be
released
in
ispLEVER
should
be
used.
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OR4E02-3BM416C 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
OR4E02-3BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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