參數(shù)資料
型號： OR4E02-2BM680I
英文描述： FPGA
中文描述： FPGA的
文件頁數(shù)： 37/153頁
文件大?。?/td> 2737K
代理商： OR4E02-2BM680I
Lattice Semiconductor
37
Data Sheet
November, 2002
ORCA
Series 4 FPGAs
Programmable Input/Output Cells
(continued)
I/O Banks and Groups
Flexible I/O features allow the user to select the type of
I/O needed to meet different high-speed interface
requirements and these I/Os require different input ref-
erences or supply voltages. The perimeter of the device
is divided into eight banks of PIO buffers, as shown in
Figure 23, and for each bank there is a separate V
DD
IO
that supplies the correct input and output voltage for a
particular standard. The user must supply the appropri-
ate power supply to the V
DD
IO pin. Within a bank, sev-
eral I/O standards may be mixed as long as they use a
common V
DD
IO. The shaded section of the I/O banks in
Figure 23 (banks 2, 3, and 4) are removed for FPSCs,
to allow the embedded block to be placed on the side
of the FPGA array. Bank 1 and bank 5 are also
extended to the corners in FPSCs to incorporate more
FPGA I/Os.
Some interface standards require a speci
fi
ed threshold
voltage known as V
REF.
To accommodate various V
REF
requirements, each bank is further divided into groups.
In these modes, where a particular V
REF
is required,
the device is automatically programmed to dedicate a
V
REF
pin for each group of PIOs within a bank. The
appropriate V
REF
voltage must be supplied by the user
and connected to the V
REF
pin for each group. The
V
REF
is dedicated exclusively to the group and cannot
be intermixed within the group with other signaling
requiring other V
REF
voltages. However, pins not
requiring V
REF
can be mixed in the same group. When
used to supply a reference voltage the V
REF
pad is no
longer available to the user for general use. The V
REF
inputs should be well isolated to keep the reference
voltage at a consistent level.
Table
17
. Compatible Mixed I/O Standards
0205(F).
Figure 23
. ORCA
High-Speed I/O Banks
Differential I/O (LVDS and LVPECL)
Series 4 devices support differential input, output, and
input/output capabilities through pairs of PIOs. The two
standards supported are LVDS and LVPECL.
The LVDS differential pair I/O standard allows for high-
speed, low-voltage swing and low-power interfaces
de
fi
ned by industry standards:
ANSI/TIA/EIA-644
and
IEEE 1596.3 SSI-LVDS
. The general purpose standard
is supplied without the need for an input reference sup-
ply and uses a low switching voltage which translates
to low ac power dissipation.
The
ORCA
LVDS I/O provides an integrated 100
ter-
mination resistor used to provide a differential voltage
across the inputs of the receiver. The on-chip integra-
tion provides termination of the LVDS receiver without
the need of discrete external board resistors. The user
has the programmable option to enable termination per
receiver pair for point-to-point applications or in multi-
point interfaces limit the use of termination to bussed
pairs. If the user chooses to terminate any differential
receiver, a single LVDS_R pin is dedicated to connect a
single 100
(± 1%) resistor to V
SS
which then enables
an internal resistor matching circuit to provide a bal-
ance 100
(± 10%) termination across all process,
voltage, and temperature. Experiments have also
shown that enabling this 100
matching resistor for
LVDS outputs also improves performance.
V
DD
IO
Bank
Voltage
3.3
V
Compatible
Standards
LVTTL,
SSTL3-I,
SSTL3-II,
GTL+,
GTL,
LVPECL,
PECL
LVCMOS2,
SSTL2-I,
SSTL2-II,
LVDS
LVCMOS18
HSTL
I,
HSTL
III,
HSTL
IV
2.5
V
1.8
V
1.5
V
PLC ARRAY
(TC)
(TL)
(BC)
(BL)
(
BANK 0
BANK 1
BANK 5
BANK 6
B
(TR)
(BR)
(
BANK 2
B
BANK 4
相關(guān)PDF資料
PDF描述
OR4E02-3BA352C FPGA
OR4E02-3BM416C FPGA
OR4E02-3BM680C FPGA
OR4E04-1BA352C FPGA
OR4E04-1BA352I FPGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
OR4E02-3BA352C 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR4E02-3BM416C 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR4E02-3BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR4E04 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:ORCASeries 4 FPGAs
OR4E04-1BA3521 制造商:Rochester Electronics LLC 功能描述: 制造商:Lattice Semiconductor Corporation 功能描述:
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*