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| 型號： | OR4E02-2BM680I |
| 英文描述： | FPGA |
| 中文描述： | FPGA的 |
| 文件頁數(shù)： | 77/153頁 |
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| 代理商： | OR4E02-2BM680I |
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Lattice Semiconductor
77
Data Sheet
November, 2002
ORCA
Series 4 FPGAs
Power
Estimation
A spreadsheet is available in ispLEVER for detailed
power estimates based on circuit implementation
details from ispLEVER and user inputs. A quick esti-
mate of power dissipation for a Series 4 device is now
presented.
Estimating Power Dissipation
The total operating power dissipated is estimated by
adding the standby (I
DD
SB), internal, and external
power dissipated. The internal and external power is
the power consumed in the PLCs and PICs, respec-
tively. In general, the standby power is small and may
be neglected. The total operating power is as follows:
P
T
=
Σ
P
INT
+
Σ
P
IO
+ P
CLK
The internal operating power is made up of two parts:
clock generation and PFU/EBR/PIO power. The PFU/
EBR/PIO power can be estimated per output based
upon the number of PFU/EBR/PIO outputs switching
when driving a typical fanout (three X6 lines and nine
X1 lines).
P
INT
= 0.015 mW/MHz
For each PFU/EBR/PIO output that switches, 0.015
mW/MHz needs to be multiplied times the frequency (in
MHz) that the output switches. Generally, this can be
estimated by using the clock rate multiplied by some
activity factor; for example, 20%.
The power dissipated by clocks is due to either global
primary clock networks or secondary/edge clock net-
works. Their power has a
fi
xed component and a vari-
able component based on the number of PFUs, PIOs,
or EBRs that use that clock as follows:
■
Primary: 0.143 mW/MHz + (0.0033mW/MHz x num-
ber of blocks driven)
■
Secondary: 0.06 mW/MHz + (0.0029mW/MHz x
number of blocks driven)
Clock power is calculated from these equations by mul-
tiplying times the clock frequency in MHz. Note that an
activity factor (i.e., 100% activity) is not used to calcu-
late clock power.
The device I/O power dissipated is the sum of the
power dissipated in the four PIOs in the PIC. This con-
sists of power dissipated by inputs and ac power dissi-
pated by outputs. The power dissipated in each PIO
depends on whether it is con
fi
gured as an input, out-
put, or input/output. If a PIO is operating as an output,
then there is a power dissipation component for P
IN
, as
well as P
OUT
. This is because the output feeds back to
the input.
The power dissipated by a LVCMOS2 input buffer is
(V
IH
= V
DD
– 0.3 V or higher) estimated as:
P
IN
= 0.09 mW/MHz
The ac power dissipation from a LVCMOS2 output or
bidirectional is estimated by the following:
P
OUT
= (C
L
+ 5.0 pF) x V
DD2
x F Watts
where the unit for C
L
(the output capacitive load) is Far-
ads, and the unit for F is Hz.
For all other I/O buffer types other than LVCMOS2, see
the detailed power estimation spreadsheet available in
ispLEVER.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR4E02-3BA352C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR4E02-3BM416C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR4E02-3BM680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR4E04 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:ORCASeries 4 FPGAs |
| OR4E04-1BA3521 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Lattice Semiconductor Corporation 功能描述: |
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