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| 型號(hào)： | OR4E02-2BM680I |
| 英文描述： | FPGA |
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Lattice Semiconductor
103
Data Sheet
November, 2002
ORCA
Series 4 FPGAs
Pin Information
(continued)
Table 65. Pin Descriptions
(continued)
Symbol
I/O
Description
Special-Purpose Pins
(continued)
WR/MPI_RW
I
WR is used in asynchronous peripheral mode. A low on WR transfers data on D[7:0] to the
FPGA.
In MPI mode, a high on MPI_RW allows a read from the data bus, while a low causes a write
transfer to the FPGA.
I/O After con
fi
guration, if the MPI is not used, WR/MPI_RW is a user-programmable I/O pin.*
I
During MPI mode the PPC_A[14:31] are used as the address bus driven by the
PowerPC
bus master utilizing the least-signi
fi
cant bits of the
PowerPC
32-bit address.
I
MPI_BURST is driven low to indicate a burst transfer is in progress in MPI mode. Driven high
indicates that the current transfer is not a burst.
I
MPI_BDIP is driven by the
PowerPC
processor in MPI mode. Assertion of this pin indicates
that the second beat in front of the current one is requested by the master. Negated before
the burst transfer ends to abort the burst data phase.
I
MPI_TSZ[0:1] signals are
driven by the bus master in MPI mode to indicate the data transfer
size for the transaction. Set 01 for byte, 10 for half-word, and 00 for word.
O
During master parallel mode A[21:0] address the con
fi
guration EPROMs up to 4M bytes.
I/O If not used for MPI these pins are user-programmable I/O pins after con
fi
guration.*
O
In
MPI
mode this is driven low indicating the MPI received the data on the write cycle or
returned data on a read cycle.
I/O If not used for MPI these pins are user-programmable I/O pins after con
fi
guration.*
I
This is the
PowerPC
synchronous, positive-edge bus clock used for the
MPI
interface. It can
be a source of the clock for the embedded system bus. If MPI is used this will be the
AMBA
bus clock.
I/O If not used for MPI these pins are user-programmable I/O pins after con
fi
guration.*
O
A low on the MPI transfer error acknowledge indicates that the MPI detects a bus error on
the internal system bus for the current transaction.
I/O If not used for MPI these pins are user-programmable I/O pins after con
fi
guration.*
O
This pin requests the MPC860 to relinquish the bus and retry the cycle.
I/O If not used for MPI these pins are user-programmable I/O pins after con
fi
guration.*
I/O Selectable data bus width from 8, 16, 32-bit in MPI mode. Driven by the bus master in a write
transaction and driven by MPI in a read transaction.
I
D[7:0] receive con
fi
guration data during master parallel, peripheral, and slave parallel con
fi
g-
uration modes when WR is low and each pin has a pull-up enabled. During serial con
fi
gura-
tion modes, D0 is the DIN input.
O
D[7:3] output internal status for asynchronous peripheral mode when RD is low.
I/O After con
fi
guration, if MPI is not used, the pins are user-programmable I/O pins.*
I/O Selectable parity bus width in MPI mode from 1, 2, 4-bit, DP[0] for D[0:7], DP[1] for D[8:15],
DP[2] for D[16:23], and DP[3] for D[24:31].
After con
fi
guration, if MPI is not used, the pins are user-programmable I/O pin.*
* The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE release
is controlled by one set of bit stream options, and the timing of the simultaneous release of all other con
fi
guration pins (and the activation of all
user I/Os) is controlled by a second set of options.
PPC_A[14:31]
MPI_BURST
MPI_BDIP
MPI_TSZ[0:1]
A[21:0]
MPI_ACK
MPI_CLK
MPI_TEA
MPI_RTRY
D[0:31]
DP[0:3]
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OR4E02-3BA352C | FPGA |
| OR4E02-3BM416C | FPGA |
| OR4E02-3BM680C | FPGA |
| OR4E04-1BA352C | FPGA |
| OR4E04-1BA352I | FPGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR4E02-3BA352C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR4E02-3BM416C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR4E02-3BM680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR4E04 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:ORCASeries 4 FPGAs |
| OR4E04-1BA3521 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Lattice Semiconductor Corporation 功能描述: |
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