參數(shù)資料
型號： OR4E02-2BM680I
英文描述： FPGA
中文描述： FPGA的
文件頁數(shù)： 102/153頁
文件大小： 2737K
代理商： OR4E02-2BM680I
102
Lattice Semiconductor
Data Sheet
November, 2002
ORCA
Series 4 FPGAs
Pin Information
(continued)
Table 65. Pin Descriptions
(continued)
Symbol
I/O
Description
Special-Purpose Pins
M[3:0]
I
During powerup and initialization, M0—M3 are used to select the con
fi
guration mode with
their values latched on the rising edge of
INIT
. During con
fi
guration, a pull-up is enabled.
I/O After con
fi
guration, these pins are user-programmable I/O.*
I
Semi-dedicated PLL clock pins. During con
fi
guration they are 3-stated with a pull up.
I/O These pins are user-programmable I/O pins if not used by PLLs after con
fi
guration.
I
Pins dedicated for the primary clock. Input pins on the middle of each side with differential
pairing.
I/O After con
fi
guration these pins are user programmable I/O, if not used for clock inputs.
I
If boundary-scan is used, these pins are test data in, test clock, and test mode select
inputs. If boundary-scan is not selected, all boundary-scan functions are inhibited once
con
fi
guration is complete. Even if boundary-scan is not used, either TCK or TMS must be
held at logic 1 during con
fi
guration. Each pin has a pull-up enabled during con
fi
guration.
I/O After con
fi
guration, these pins are user-programmable I/O in boundary scan is not used.*
O
During con
fi
guration in asynchronous peripheral mode, RDY/RCLK indicates another byte
can be written to the FPGA. If a read operation is done when the device is selected, the
same status is also available on D7 in asynchronous peripheral mode.
During the master parallel con
fi
guration mode, RCLK is a read output signal to an exter-
nal memory. This output is not normally used.
I/O After con
fi
guration this pin is a user-programmable I/O pin.*
O
High during con
fi
guration is output high until con
fi
guration is complete. It is used as a con-
trol output, indicating that con
fi
guration is not complete.
I/O After con
fi
guration, this pin is a user-programmable I/O pin.*
O
Low during con
fi
guration
is output low until con
fi
guration is complete. It is used as a control
output, indicating that con
fi
guration is not complete.
I/O After con
fi
guration, this pin is a user-programmable I/O pin.*
I/O
INIT
is a bidirectional signal before and during con
fi
guration. During con
fi
guration, a pull-
up is enabled, but an external pull-up resistor is recommended. As an active-low open-
drain output,
INIT
is held low during power stabilization and internal clearing of memory.
As an active-low input,
INIT
holds the FPGA in the wait-state before the start of con
fi
gura-
tion.
After con
fi
guration, this pin is a user-programmable I/O pin.*
I
CS0
and CS1 are used in the asynchronous peripheral, slave parallel, and microprocessor
con
fi
guration modes. The FPGA is selected when
CS0
is low and CS1 is high. During con-
fi
guration, a pull-up is enabled.
I/O After con
fi
guration, if MPI is not used, these pins are user-programmable I/O pins.*
I
RD
is used in the asynchronous peripheral con
fi
guration mode. A low on
RD
changes
D[7:3] into a status output.
WR
and
RD
should not be used simultaneously. If they are, the
write strobe overrides.
This pin is also used as the
MPI
data transfer strobe. As a status indication, a high indicates
ready, and a low indicates busy.
I/O After con
fi
guration, if the
MPI
is not used, this pin is a user-programmable I/O pin.*
* The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE release
is controlled by one set of bit stream options, and the timing of the simultaneous release of all other con
fi
guration pins (and the activation of all
user I/Os) is controlled by a second set of options.
PLL_CK[0:7][TC]
P[TBLR]CLK[1:0][TC]
TDI, TCK, TMS
RDY/BUSY/RCLK
HDC
LDC
INIT
CS0, CS1
RD/MPI_STRB
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