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| 型號： | OR4E02-2BM680I |
| 英文描述： | FPGA |
| 中文描述： | FPGA的 |
| 文件頁數(shù)： | 38/153頁 |
| 文件大?。?/td> | 2737K |
| 代理商： | OR4E02-2BM680I |
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38
Lattice Semiconductor
Data Sheet
November, 2002
ORCA
Series 4 FPGAs
Programmable Input/Output Cells
(continued)
High-Speed Memory Interfaces
PIO features allow high-speed interfaces to external
SRAM and/or DRAM devices. Series 4 I/O meet
200 MHz
ZBT
requirements when switching between
write and read cycles.
ZBT
allows 100% use of bus
cycles during back-to-back read/write and write/read
cycles. However this maximum utilization of the bus
increases probability of bus contention when the inter-
faced devices attempt to drive the bus to opposite logic
values. The LVTTL I/O interfaces directly with commer-
cial
ZBT
SRAMs signalling and allows the versatility to
program the FPGA drive strengths from 6 mA to
24 mA.
DDR allows data to be read on both the rising and the
falling edge of the clock which delivers twice the band-
width. DDR doubles the memory speed from SDRAMs
or SRAMs without the need to increase clock fre-
quency. The
fl
exibility of the PIO allows at least
156 MHz/312 Mbits per second performance using the
SSTL I/O or HSTL I/O features of the Series 4 devices.
High-Speed Networking Interfaces
Series 4 devices support many I/O standards used in
networking. Two examples of this are the XGMII stan-
dard for 10 GbE (HSTL or SSTL I/Os) and the SPI-4
standard for various 10 Gbits/s network interfaces
(LVDS I/Os). Both operate as a point-to-point link
between devices that are forward clocked and transmit
data on both clock edges (DDR). The XGMII interface
is 36-bits wide per data
fl
ow direction and the SPI-4
interface is a 16-bit interface. The XGMII speci
fi
cation
is 156 MHz/312 Mbits/s and the SPI-4 speci
fi
cation that
can be met is 325 MHz/650 Mbits/s. More information
about using
ORCA
for these applications can be found
in the associated application note.
Bus Hold
Each PIO can be programmed with a KEEPERMODE
feature. This element is user programmed for bus hold
requirements. This mode retains the last known state of
a bus when the bus goes into 3-state. It prevents
fl
oat-
ing busses and saves system power.
PIO Downlink/Uplink (Shift Registers)
Each group of four PIOs in a PIC have access to an
input/output shift register as shown in Figure 24. This
feature allows high-speed input data to be divided
down by 1/2 or 1/4 and output data can be multiplied by
2x or 4x its internal speed. Both the input and output
shift registers can be programmed to operate at the
same time and are controlled by the same clock and
control signals.
For input shift mode, the data from INDD from the PIO
is connected to the input shift register. The input data is
divided down and is driven to the routing through the
INSH nodes. For output shift mode, the data from the
OUTSH nodes are driven from the internal routing and
connects to the output shift register. This output data is
multiplied up and driven to the OUTDD signal on the
PIOs.
In 2x output mode or input mode, two of the four I/Os in
a PIC can use the shift registers. While in 4x mode,
only one I/O can use the shift registers. This also
means that all differential I/Os on a Series 4 device can
use 2x shift register mode, but 4x mode is only avail-
able for half of the differential I/Os.
In 4x input mode, all the INSH nodes are used, while 2x
mode uses INSH4 and INSH3 for one shift register and
INSH2 and INSH1 for the second shift register. Simi-
larly, the output shift register in 4x mode uses all the
OUTSH signals. OUTSH2 and OUTSH1 are used for
2x output mode for one shift register and OUTSH4 and
OUTSH3 are used for the other output shift register.
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| OR4E04-1BA352C | FPGA |
| OR4E04-1BA352I | FPGA |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| OR4E02-3BA352C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR4E02-3BM416C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR4E02-3BM680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR4E04 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:ORCASeries 4 FPGAs |
| OR4E04-1BA3521 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Lattice Semiconductor Corporation 功能描述: |
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