參數(shù)資料
型號： OR4E02-2BM680I
英文描述： FPGA
中文描述： FPGA的
文件頁數(shù)： 35/153頁
文件大?。?/td> 2737K
代理商： OR4E02-2BM680I
Lattice Semiconductor
35
Data Sheet
November, 2002
ORCA
Series 4 FPGAs
Programmable Input/Output Cells
(continued)
Inputs
There are many major options on the PIO inputs that
can be selected in the ispLEVER tools listed in Table
14. Inputs may have a pull-up or pull-down resistor
selected on an input for signal stabilization and power
management. Input signals in a PIO are passed to CIB
routing and/or a fast route into the clock routing sys-
tem. A fast input from one PIO per PIC is also available
to drive the edge clock network for fast I/O timing to
other nearby PIOs.
There is also a programmable delay available on the
input. When enabled, this delay affects the INFF and
INDD signals of each PIO, but not the clock input. The
delay allows any signal to have a guaranteed zero hold
time when input.
Inputs should have transition times of less than 100 ns
and should not be left
fl
oating. For full swing inputs, the
timing characterization is done for rise/fall times of
≥
1 V/ns. If any pin is not used, it is 3-stated with an
internal pull-up resistor enabled automatically after
con
fi
guration. Floating inputs increase power con-
sumption, produce oscillations, and increase system
noise. The inputs in LVTTL, LVCMOS2, and
LVCMOS18 modes have a typical hysteresis of approx-
imately 250 mV to reduce sensitivity to input noise. The
PIC contains input circuitry which provides protection
against latch-up and electrostatic discharge.
The other features of the PIO inputs relate to the latch/
FF structure in the input path. In latch mode, the input
signal is fed to a latch that is clocked by either the pri-
mary, secondary, or edge clock signal. The clock may
be inverted or noninverted. There is also a local set/
reset signal to the latch. The senses of these signals
are also programmable as well as the capability to
enable or disable the global set/reset signal and select
the set/reset priority. The same control signals may
also be used to control the input latch/FF when it is
con
fi
gured as a FF instead of a latch, with the addition
of another control signal used as a clock enable. The
PIOs are paired together and have independent CE,
Set/reset, and GSRN control signals per PIO pair.
There are two options for zero-hold input capture in the
PIO. If input delay mode is selected to delay the signal
from the input pin, data can be either registered or
latched with guaranteed zero-hold time in the PIO
using a global primary system clock. The fast zero-hold
mode of the PIO input takes advantage of a latch/FF
combination to latch the data quickly for zero-hold
using a fast edge clock before passing the data to the
FF which is clocked by a global primary system clock.
The combination of input register capability with non-
registered inputs provides for input signal demultiplex-
ing without any additional resources. The PIO input
signal is sent to both the input register and directly to
the unregistered input (INDD). The signal is latched
and output to routing at INFF. These signals may then
be registered or otherwise processed in the PLCs.
Every PIO input can also perform input double data
rate (DDR) functions with no PLC resources required.
This type of scheme is necessary for DDR applications
which require data to be clocked in from the I/O on both
edges of the clock. In this scheme the input of INFF
and INSH are captured on the positive and negative
edges of the clock.
Table 14. PIO Options
Input
Option
Input
Speed
Float
Value
Register
Mode
Fast,
Delayed,
Normal
Pull-up,
Pull-down,
None
Latch,
FF,
Fast
Zero
Hold
FF,
None
(direct
input)
Inverted,
Noninverted
Clock
Sense
Keeper
Mode
on,
off
LVDS
Resistor
on,
off
Output
Option
Output
Speed
Output
Drive
Current
Output
Function
Output
Sense
3-State
Sense
Clock
Sense
Logic Options
I/O
Controls
Fast,
Slew
12
mA/6
mA,
6
mA/3
mA,
or
24
mA/12
mA
Normal,
Fast
Open
Drain
Active-high,
Active-low
Active-high,
Active-low
Inverted,
Noninverted
See Table 15
Option
Clock
Enable
Active-high,
Active-low,
Always
Enabled
Active-high,
Active-low,
No
Local
Reset
Synchronous,
Asynchronous
CE
over
LSR,
LSR
over
CE
Enable
GSR,
Disable
GSR
Set/Reset
Level
Set/Reset
Type
Set/Reset
Priority
GSR
Control
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