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| 型號： | OR4E02-2BM680I |
| 英文描述： | FPGA |
| 中文描述： | FPGA的 |
| 文件頁數(shù)： | 33/153頁 |
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| 代理商： | OR4E02-2BM680I |
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Lattice Semiconductor
33
Data Sheet
November, 2002
ORCA
Series 4 FPGAs
Programmable Input/Output Cells
(continued)
Table 13. Series 4 Programmable I/O Standards
Note: interfaces to DDR and
ZBT
memories are supported through the interface standards shown above.
The PIOs are located along the perimeter of the device. The PIO name is represented by a two-letter designation to
indicate the side of the device on which it is located followed by a number to indicate the row or column in which it is
located. The
fi
rst letter, P, designates that the cell is a PIO and not a PLC. The second letter indicates the side of the
array where the PIO is located. The four sides are left (L), right (R), top (T), and bottom (B). A number follows to
indicate the PIC row or column. The individual I/O pad is indicated by a single letter (either A, B, C, or D) placed at
the end of the PIO name. As an example, PL10A indicates a pad located on the left side of the array in the tenth
row.
Each PIC interfaces to four bond pads through four PIOs and contains the necessary routing resources to provide
an interface between I/O pads and the CIBs. Each PIC contains input buffers, output buffers, routing resources,
latches/FFs, and logic and can be con
fi
gured as an input, output, or bidirectional I/O. Any PIO is capable of sup-
porting the I/O standards listed in Table 13.
The CIBs that connect to the PICs have signi
fi
cant local routing resources, similar to routing in the PLCs. This new
routing increases the ability to
fi
x user pinouts prior to placement and routing of a design and still maintain routabil-
ity. The
fl
exibility provided by the routing also provides for increased signal speed due to a greater variety of optimal
signal paths.
Included in the routing interface is a fast path from the input pins to the PFU logic. This feature allows for input sig-
nals to be very quickly processed by the SLIC decoder function and used on-chip or sent back off of the FPGA.
A diagram of a single PIO is shown in Figure 22, and Table 14 provides an overview of the programmable functions
in an I/O cell.
Standard
LVTTL
LVCMOS2
LVCMOS18
PCI
LVDS
Bused-LVDS
V
DD
IO (V)
3.3
2.5
1.8
3.3
2.5
2.5
V
REF
(V)
NA
NA
NA
NA
NA
NA
Interface Usage
General purpose.
PCI.
Point to point and multi-drop backplanes, high noise immunity.
Network backplanes, high noise immunity, bus architecture
backplanes.
Network backplanes, differential 100 MHz+ clocking, optical
transceiver, high-speed networking.
Backplanes.
Backplane or processor interface.
LVPECL
3.3
NA
PECL
GTL
GTL+
3.3
3.3
3.3
1.5
1.5
3.3
2.5
2.0
0.8
1.0
0.75
0.9
1.5
1.25
HSTL-class I
HTSL-class III and IV
STTL3-class I and II
SSTL2-class I and II
High-speed SRAM and networking interfaces.
Synchronous DRAM interface.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| OR4E02-3BA352C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR4E02-3BM416C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR4E02-3BM680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR4E04 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:ORCASeries 4 FPGAs |
| OR4E04-1BA3521 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Lattice Semiconductor Corporation 功能描述: |
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