參數(shù)資料
型號： OR4E02-2BM680I
英文描述： FPGA
中文描述： FPGA的
文件頁數(shù)： 73/153頁
文件大小： 2737K
代理商： OR4E02-2BM680I
Lattice Semiconductor
73
Data Sheet
November, 2002
ORCA
Series 4 FPGAs
FPGA Con
fi
guration Modes
(continued)
5-4487(F).a
Figure 45. Slave Parallel Con
fi
guration Schematic
Daisy-Chaining
Multiple FPGAs can be con
fi
gured by using a daisy-chain of the FPGAs. Daisy-chaining uses a lead FPGA and one
or more FPGAs con
fi
gured in slave serial mode. The lead FPGA can be con
fi
gured in any mode except slave paral-
lel mode.
All daisy-chained FPGAs are connected in series. Each FPGA reads and shifts the preamble and length count in on
positive CCLK and out on positive CCLK edges.
An upstream FPGA that has received the preamble and length count outputs a high on DOUT until it has received
the appropriate number of data frames so that downstream FPGAs do not receive frame start indications. After
loading and retransmitting the preamble and length count to a daisy-chain of slave devices, the lead device loads its
con
fi
guration data frames. The loading of con
fi
guration data continues after the lead device has received its con
fi
g-
uration data if its internal frame bit counter has not reached the length count. When the con
fi
guration RAM is full
and the number of bits received is less than the length count
fi
eld, the FPGA shifts any additional data out on
DOUT.
The con
fi
guration data is read into DIN of slave devices on the positive edge of CCLK, and shifted out DOUT on the
positive edge of CCLK. Figure 46 shows the connections for loading multiple FPGAs in a daisy-chain con
fi
guration.
The generation of CCLK for the daisy-chained devices that are in slave serial mode differs depending on the con
fi
g-
uration mode of the lead device. A master parallel mode device uses its internal timing generator to produce an
internal CCLK at eight times its memory address rate (RCLK). The asynchronous peripheral mode and MPI mode
device outputs eight CCLKs for each write cycle. If the lead device is con
fi
gured in slave mode, CCLK must be
routed to the lead device and to all of the daisy-chained devices.
MICRO-
PROCESSOR
OR
SYSTEM
D[7:0]
DONE
INIT
CCLK
CS1
CS0
WR
M2
M1
M0
HDC
LDC
8
V
DD
PRGM
ORCA
FPGA
M3
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OR4E02-3BA352C 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
OR4E02-3BM416C 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
OR4E02-3BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
OR4E04 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:ORCASeries 4 FPGAs
OR4E04-1BA3521 制造商:Rochester Electronics LLC 功能描述: 制造商:Lattice Semiconductor Corporation 功能描述:
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