參數(shù)資料
型號： OR4E02-2BM680I
英文描述： FPGA
中文描述： FPGA的
文件頁數(shù)： 36/153頁
文件大小： 2737K
代理商： OR4E02-2BM680I
36
Lattice Semiconductor
Data Sheet
November, 2002
ORCA
Series 4 FPGAs
Programmable Input/Output Cells
(continued)
Outputs
The PIO’s output drivers have programmable drive
capability and slew rates. Two propagation delays (fast,
slewlim) are available on output drivers. There are
three combinations of programmable drive currents
(24 mA sink/12 mA source, 12 mA sink/6 mA source,
and 6 mA sink/3 mA source). At powerup, the output
drivers are in slewlim mode with 12mA sink/6 mA
source. If an output is not to be driven in the selected
con
fi
guration mode, it is 3-stated with a pullup resistor.
The output buffer signal can be inverted, and the
3-state control signal can be made active-high, active-
low, or always enabled. In addition, this 3-state signal
can be registered or nonregistered. Additionally, there
is a fast, open-drain output option that directly connects
the output signal to the 3-state control, allowing the out-
put buffer to either drive to a logic 0 or 3-state, but
never to drive to a logic 1.
Every PIO output can perform output data multiplexing
with no PLC resources required. This type of scheme is
necessary for DDR applications which require data
clocking out of the I/O on both edges of the clock. In
this scheme the OUTFF and OUTSH are registered
and sent out on both the positive and negative edges of
the clock using an output multiplexor. This multiplexor
is controlled by either the edge clock or system clock.
This multiplexor can also be con
fi
gured to select
between one registered output from OUTFF and one
nonregistered output from OUTDD.
The PIC logic block can also generate logic functions
based on the signals on the OUTDD and CLK ports of
the PIO. The functions are AND, NAND, OR, NOR,
XOR, and XNOR. Table 15 is provided as a summary
of the PIO logic options.
Table 15.
PIO
Logic
Options
PIO Register Control Signals
The PIO latches/FFs have various clock, clock enable
(CE), local set/reset (LSR), and GSRN controls. Table
16 provides a summary of these control signals and
their effect on the PIO latches/FFs. Note that all control
signals are optionally invertible.
Table 16. PIO Register Control Signals
Option
AND
Description
Output
logical
AND
of
signals
on
OUTDD
and
clock.
Output
logical
NAND
of
signals
on
OUTDD
and
clock.
Output
logical
OR
of
signals
on
OUTDD
and
clock.
Output
logical
NOR
of
signals
on
OUTDD
and
clock.
Output
logical
XOR
of
signals
on
OUTDD
and
clock.
Output
logical
XNOR
of
signals
on
OUTDD
and
clock.
NAND
OR
NOR
XOR
XNOR
Control
Signal
Edge
Clock
(ECLK)
Effect/Functionality
Clocks
input
fast-capture
latch;
option-
ally
clocks
output
FF,
or
3-state
FF,
or
PIO
shift
registers.
Clocks
input
latch/FF;
optionally
clocks
output
FF,
or
3-state
FF,
or
PIO
shift
registers.
Optionally
enables/disables
input
FF
(not
available
for
input
latch
mode);
optionally
enables/disables
output
FF;
separate
CE
inversion
capability
for
input
and
output.
Option
to
disable;
affects
input
latch/FF,
output
FF,
and
3-state
FF
if
enabled.
Option
to
enable
or
disable
per
PIO
after
initial
configuration.
System
Clock
(SCLK)
Clock
Enable
(CE)
Local
Set/
Reset
(LSR)
Global
Set/
Reset
(GSRN)
Set/Reset
Mode
The
input
latch/FF,
output
FF,
and
3-
state
FF
are
individually
set
or
reset
by
both
the
LSR
and
GSRN
inputs.
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