參數(shù)資料
型號： OR4E02-2BM680I
英文描述： FPGA
中文描述： FPGA的
文件頁數(shù)： 88/153頁
文件大?。?/td> 2737K
代理商： OR4E02-2BM680I
88
Lattice Semiconductor
Data Sheet
November, 2002
ORCA
Series 4 FPGAs
Timing
Characteristics
(continued)
Table
53.
Secondary
CLK
(SCLK)
Setup/Hold
Time
without
on-chip
PLLs
(Pin-to-Pin)
OR4Exx commercial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C
<
TJ
<
+85 °C
OR4Exx industrial: VDD15 = 1.425 V to 1.575 V, VDD33 = 3.0 V to 3.6 V, VDDIO = 3.0 V to 3.6 V, –40 °C
<
TJ
<
+100 °C
Notes:
1. The
pin-to-pin
timing
parameters
in
this
table
will
match
ispLEVER
if
the
clock
delay
multiplier
in
the
setup
preference
is
set
to
0.95
for
setup
time
and
1.05
for
hold
time.
2. Timing
is
without
the
use
of
the
phase-locked
loops
(PLLs)
or
PIO
input
FF
cycle
stealing
delays
(which
can
provide
reductions
in
setup
time
at
the
expense
of
hold
time).
3. This
setup/hold
time
is
for
a
fully
routed
clock
tree
that
uses
the
secondary
clock
network.
It
includes
both
the
LVTTL
(3.3
V)
input
clock
buffer
delay,
the
clock
routing
to
the
PIO
CLK
input,
the
setup/hold
time
of
the
PIO
FF
(with
the
data
input
delay
disabled)
and
the
LVTTL
(3.3
V)
input
data
buffer
to
PIO
FF
delay.
An
SCLK
input
clock
can
be
at
any
input
pin.
4. For
timing
improvements
using
other
I/O
buffer
types
for
the
input
clock
buffer
or
input
data
buffer,
see
Table
45.
5. The
ORT8850H
FPSC
has
slightly
reduced
performance
from
the
values
in
this
table.
ispLEVER
will
report
the
actual
delay
values
for
all
devices,
including
the
ORT8850H
in
this
arrangement.
5-4847(F).b
Figure
50.
Input
to
Secondary
CLK
Setup/Hold
Time
Description
Device
Speed
Unit
-1
-2
-3
Min
5.95
Max
—
Min
5.54
Max
—
Min
5.06
Max
—
Input
to
SCLK
Setup
Time
(Input
within
6
PICs
of
SCLK
input),
Fast
Capture
Enabled
Input
to
SCLK
Setup
Time
(Input
within
6
PICs
of
SCLK
input),
No
Input
Data
Delay
Reduced
Setup
Time
per
each
extra
6
PICs
per
clock
route
direction.
Input
to
SCLK
Hold
Time
(Input
within
6
PICs
of
SCLK
input),
Fast
Capture
Enabled
Input
to
SCLK
Hold
Time
(Input
within
6
PICs
of
SCLK
input),
No
Input
Data
Delay
Additional
Hold
Time
per
each
extra
6
PICs
per
clock
route
direction.
Input
Delay
Adjustments
from
PIO
Cycle
Stealing
(typically
used
to
reduce
setup
time
by
the
min
value
shown):
One
Delay
Cell
Two
Delay
Cells
Three
Delay
Cells
All
ns
All
0.00
—
0.00
—
0.00
—
ns
All
0.36
—
0.38
—
0.34
—
ns
All
0.00
—
0.00
—
0.00
—
ns
All
3.07
—
3.04
—
2.74
—
ns
All
0.36
—
0.38
—
0.34
—
ns
ICYCDEL1
ICYCDEL2
ICYCDEL3
—
—
—
0.89
1.64
2.43
—
—
—
0.70
1.29
1.98
—
—
—
0.64
1.18
1.80
ns
ns
ns
Q
D
SCLK
INPUT
PIO
FF
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