參數(shù)資料
型號： OR4E02-2BM680I
英文描述： FPGA
中文描述： FPGA的
文件頁數(shù)： 63/153頁
文件大?。?/td> 2737K
代理商： OR4E02-2BM680I
Lattice Semiconductor
63
Data Sheet
November, 2002
ORCA
Series 4 FPGAs
Con
fi
guration Data Format
(continued)
Table 31. Con
fi
guration Frame Format and Contents
Table 31A. Con
fi
guration Frame Format and Contents for Embedded Block RAM
Frame
Contents
11110010
24-bit length count
11111111
0101 1111 1111 1111
44 reserved bits
Part ID
Checksum
11111111
1111 0010
11111111
00
14-bit address
Checksum
11111111
01
Alignment bits
Description
Header
Preamble for generic FPGA.
Con
fi
guration bitstream length.
8-bit trailing header.
ID frame header.
Reserved bits set to 0.
20-bit part ID.
8-bit checksum.
8 stop bits (high) to separate frames.
This is a new mandatory header for generic portion.
8 stop bits (high) to separate frames.
Address frame header.
14-bit address of generic FPGA.
8-bit checksum.
Eight stop bits (high) to separate frames.
Data frame header. same as generic.
String of 0 bits added to frame to reach a byte bound-
ary.
Number of data bits depends upon device.
8-bit checksum.
Eight stop bits (high) to separate frames.
Postamble header, 00 =
fi
nish, 10 = more bits coming.
Dummy address.
16 stop bits (high).
ID Frame
FPGA Header
FPGA Address Frame
FPGA Data Frame
Data bits
Checksum
11111111
00 or 10
11111111 111111
11111111 11111111
Postamble for Generic
FPGA
Frame
Contents
11110001
11111111
00
6-bit address
Checksum
11111111
01
000000
512x18 data bits
Checksum
11111111
00 or 10
111111
11111111 11111111
Description
RAM Header
A mandatory header for RAM bitstream portion.
8 stop bits (high) to separate frames.
Address frame header. same as generic.
6-bit address of RAM blocks.
8-bit checksum.
Eight stop bits (high) to separate frames.
Data frame header. same as generic.
Six of 0 bits added to reach a byte boundary.
Exact number of bits in a RAM block.
8-bit checksum.
Eight stop bits (high) to separate frames.
Postamble header. 00 =
fi
nish, 10 = more bits coming.
Dummy address.
16 stop bits (high).
RAM Address Frame
RAM Data Frame
Postamble for RAM
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
OR4E02-3BA352C 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR4E02-3BM416C 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR4E02-3BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR4E04 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:ORCASeries 4 FPGAs
OR4E04-1BA3521 制造商:Rochester Electronics LLC 功能描述: 制造商:Lattice Semiconductor Corporation 功能描述:
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