參數(shù)資料
型號： OR4E02-2BM680I
英文描述： FPGA
中文描述： FPGA的
文件頁數(shù)： 41/153頁
文件大?。?/td> 2737K
代理商： OR4E02-2BM680I
Data Sheet
November, 2002
Lattice Semiconductor
41
ORCA
Series 4 FPGAs
Special Function Blocks
(continued)
5-6765(F)
Figure 26. Boundary-Scan Interface
D[7:0]
INTR
MICRO-
PROCESSOR
D[7:0]
CE
RA
R/W
DAV
INT
SP
TMS0
TCK
TDI
TDO
TDI
TMS
TCK
TDO
ORCA
SERIES
FPGA
TDI
ORCA
SERIES
FPGA
TMS
TCK
TDO
TDI
TMS
TCK
TDO
ORCA
SERIES
FPGA
BOUNDARY-
SCAN
MASTER
(BSM)
(DUT)
(DUT)
(DUT)
The boundary-scan support circuit shown in Figure 26
is the 497AA boundary-scan master (BSM). The BSM
off-loads tasks from the test host to increase test
throughput. To interface between the test host and the
DUTs, the BSM has a general MPI and provides paral-
lel-to-serial/serial-to-parallel conversion, as well as
three 8K data buffers. The BSM also increases test
throughput with a dedicated automatic test-pattern
generator and with compression of the test response
with a signature analysis register. The PC-based
boundary-scan test card/software allows a user to
quickly prototype a boundary-scan test setup.
Boundary-Scan Instructions
The Series 4 boundary-scan circuitry supports a total
of 18 instructions. This includes ten
IEEE
1149.1
,
1149.2, and 1532/D1 instructions, one optional
IEEE
1149.3 instruction, two
IEEE
1532/D1 optional instruc-
tions, and
fi
ve
ORCA
-de
fi
ned instructions. There are
also 16 other scan chain instructions that are used only
during factory device testing and will not be discussed
in this data sheet. A 6-bit wide instruction register sup-
ports all the instructions listed in Table 18.
The BYPASS instruction passes data intentionally from
TDI to TDO after being clocked by TCK.
Table 18. Boundary-Scan Instructions
Code
000000
000001
000011
000100
000101
000110
001000
001001
001010
001011
001101
001110
010001
010010
010011
010100
010101
111111
Instruction
EXTEST
SAMPLE
PRELOAD
RUNBIST
IDCODE
USERCODE
ISC_ENABLE
ISC_PROGRAM
ISC_NOOP
ISC_DISABLE
ISC_PROGRAM_USERCODE
ISC_READ
PLC_SCAN_RING1
PLC_SCAN_RING2
PLC_SCAN_RING3
RAM_WRITE
RAM_READ
BYPASS
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相關代理商/技術參數(shù)
參數(shù)描述
OR4E02-3BA352C 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
OR4E02-3BM416C 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
OR4E02-3BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
OR4E04 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:ORCASeries 4 FPGAs
OR4E04-1BA3521 制造商:Rochester Electronics LLC 功能描述: 制造商:Lattice Semiconductor Corporation 功能描述:
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