參數(shù)資料
型號(hào)： OR4E02-2BM680I
英文描述： FPGA
中文描述： FPGA的
文件頁(yè)數(shù)： 105/153頁(yè)
文件大小： 2737K
代理商： OR4E02-2BM680I
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Lattice Semiconductor
105
Data Sheet
November, 2002
ORCA
Series 4 FPGAs
Pin Information
(continued)
Package Compatibility
Table 66 provides the number of user I/Os available for the
ORCA
Series 4 FPGAs for each available package.
Each package has six dedicated con
fi
guration pins.
Table
67
thru
Table
69
provide
the
package
pin
and
pin
function
for
the
Series
4
FPGAs
and
packages.
The
bond
pad
name
is
identified
in
the
PIO
nomeclature
used
in
the
ispLEVER
design
editor.
The
Bank
column
provides
information
as
to
which
output
voltage
level
bank
the
given
pin
is
in.
The
Group
column
provides
information
as
to
the
group
of
pins
the
given
pin
is
in.
This
is
used
to
show
which
VREF
pin
is
used
to
provide
the
reference
voltage
for
single-ended
limited-swing
I/Os.
If
none
of
these
buffer
types
(such
as
SSTL,
GTL,
HSTL)
are
used
in
a
given
group,
then
the
VREF
pin
is
available
as
an
I/O
pin.
When
the
number
of
FPGA
bond
pads
exceeds
the
number
of
package
pins,
bond
pads
are
unused.
When
the
number
of
package
pins
exceeds
the
number
of
bond
pads,
package
pins
are
left
unconnected
(no
connects).
When
a
package
pin
is
to
be
left
as
a
no
connect
for
a
specific
die,
it
is
indicated
as
a
note
in
the
device
column
for
the
FPGA.
The
tables
provide
no
information
on
unused
pads.
In
order
to
allow
pin-for-pin
compatible
board
layouts
that
can
accommodate
both
devices,
some
key
compatibility
issues
include
the
following.:
■
Shared
Control
Signals
on
I/O
Registers.
The
ORCA
Series
4
architecture
shares
clock
and
control
signals
between
two
adjacent
I/O
pads.
If
I/O
registers
are
used,
incompatibilities
may
arise
between
devices
when
dif-
ferent
clock
or
control
signals
are
needed
on
adjacent
package
pins.
This
is
because
one
device
may
allow
inde-
pendent
clock
or
control
signals
on
these
adjacent
pins,
while
the
other
may
force
them
to
be
the
same.
There
are
two
ways
to
avoid
this
issue.
—
Always
keep
an
open
bonded
pin
(non-bonded
pins
do
not
count)
between
pins
that
require
different
clock
or
control
signals.
Note
that
this
open
pin
can
be
used
to
connect
signals
that
do
not
require
the
use
of
I/O
regis-
ters
to
meet
timing.
—
Place
and
route
the
design
in
all
target
devices
to
verify
they
produce
valid
designs.
Note
that
this
method
guarantees
the
current
design,
but
does
not
necessarily
guard
against
issues
that
can
occur
when
design
changes
are
made
that
affect
I/O
registers.
—
2X/4X
I/O
Shift
Registers.
If
2X
I/O
shift
registers
or
4X
I/O
shift
registers
are
used
in
the
design,
this
may
cause
incompatibilities
between
the
devices
because
only
the
A
and
C
I/Os
in
a
PIC
support
2X
I/O
shift
regis-
ters
and
only
A
I/Os
supports
4X
I/O
shift
register
mode.
A
and
C
I/Os
are
shown
in
the
following
pinout
tables
under
the
I/O
pad
columns
as
those
ending
in
A
or
C.
■
Edge Clock Input Pins.
The input buffers for fast edge clocks are only available at the C I/O pad. The C I/Os are
shown in the following pinout tables under the I/O pad columns as those ending in C.
■
680 PBGAM Differential I/O Pairs.
Note that the OR4E02 device in the 680 PBGAM package has two less dif-
ferential I/O pairs available than the OR4E04 or OR4E06, even though the total number of user I/Os are the same
for all three devices.
相關(guān)PDF資料
PDF描述
OR4E02-3BA352C FPGA
OR4E02-3BM416C FPGA
OR4E02-3BM680C FPGA
OR4E04-1BA352C FPGA
OR4E04-1BA352I FPGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
OR4E02-3BA352C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR4E02-3BM416C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR4E02-3BM680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR4E04 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:ORCASeries 4 FPGAs
OR4E04-1BA3521 制造商:Rochester Electronics LLC 功能描述: 制造商:Lattice Semiconductor Corporation 功能描述:
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