參數(shù)資料
型號(hào)： OR4E02-2BM680I
英文描述： FPGA
中文描述： FPGA的
文件頁數(shù)： 61/153頁
文件大?。?/td> 2737K
代理商： OR4E02-2BM680I
Lattice Semiconductor
61
Data Sheet
November, 2002
ORCA
Series 4 FPGAs
FPGA States of Operation
(continued)
Recon
fi
guration
To recon
fi
gure the FPGA when the device is operating
in the system, a low pulse is input into
PRGM
or one of
the program bits in the embedded system bus control
register must be set. The con
fi
guration data in the
FPGA is cleared, and the I/Os not used for con
fi
gura-
tion are 3-stated with a pullup. The FPGA then samples
the mode select inputs and begins recon
fi
guration.
When recon
fi
guration is complete, DONE is released,
allowing it to be pulled high.
Partial Recon
fi
guration
All
ORCA
device families have been designed to allow
a partial recon
fi
guration of the FPGA at any time. This
is done by setting a bit stream option in the previous
con
fi
guration sequence that tells the FPGA to not reset
all of the con
fi
guration RAM during a recon
fi
guration.
Then only the con
fi
guration frames that are to be modi-
fi
ed need to be rewritten, thereby reducing the con
fi
gu-
ration time.
Other bit stream options are also available that allow
one portion of the FPGA to remain in operation while a
partial recon
fi
guration is being done. If this is done, the
user must be careful to not cause contention between
the two con
fi
gurations (the bit stream resident in the
FPGA and the partial recon
fi
guration bit stream) as the
second recon
fi
guration bit stream is being loaded.
During a partial re-con
fi
guration where the con
fi
gura-
tion option is set to have the internal logic remain active
during con
fi
guration the internal SLJC BIDI signals will
always be 3-stated. Previous families of ORCA FPGAs
would allow the BIDIs to continue to be under user
logic control during a partial re-con
fi
guration.
Other Con
fi
guration Options
There are many other con
fi
guration options available to
the user that can be set during bit stream generation in
ispLEVER. These include options to enable boundary-
scan and/or the MPI and/or the programmable PLL
blocks, readback options, and options to control and
use the internal oscillator after con
fi
guration.
Other useful options that affect the next con
fi
guration
(not the current con
fi
guration process) include options
to disable the global set/reset during con
fi
guration, dis-
able the 3-state of I/Os during con
fi
guration, and dis-
able the reset of internal RAMs during con
fi
guration to
allow for partial con
fi
gurations (see above). For more
information on how to set these and other con
fi
guration
options, please see the ispLEVER documentation.
Con
fi
guration Data Format
The ispLEVER Development System interfaces with
front-end design entry tools and provides tools to pro-
duce a fully con
fi
gured FPGA. This section discusses
using the ispLEVER Development System to generate
con
fi
guration RAM data and then provides the details
of the con
fi
guration frame format.
Using ispLEVER to Generate Con
fi
guration
RAM Data
The con
fi
guration data bit stream de
fi
nes the I/O func-
tionality, logic, and interconnections within the FPGA.
The bit stream is generated by the development sys-
tem. The bit stream created by the bit stream genera-
tion tool is a series of 1s and 0s used to write the FPGA
con
fi
guration RAM. It can be loaded into the FPGA
using one of the con
fi
guration modes discussed later.
In bit stream generator, the designer selects options
that affect the FPGA’s functionality. Using the output of
the bit stream generator,
circuit_name.bit
, the devel-
opment system’s download tool can load the con
fi
gura-
tion data into the
ORCA
series FPGA evaluation board
from a PC or workstation.
A download cable that can be used to download from
any PC or workstation supported by ispLEVER is avail-
able. This cable allows download to an FPGA that can
be programmed via the serial con
fi
guration interface
(requiring the mode pins to be set) or the JTAG bound-
ary scan interface (not requiring the setting of mode
pins). The lead device can then program other FPGAs
or FPSCs on the board via daisy-chaining.
Alternatively, a user can program a PROM (such as a
Serial ROM or a standard EPROM) and load the FPGA
from the PROM. The development system’s PROM
programming tool produces a
fi
le in .mcs, .tek or .exo
format.
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