參數(shù)資料
型號： OR4E02-2BM680I
英文描述： FPGA
中文描述： FPGA的
文件頁數(shù)： 49/153頁
文件大?。?/td> 2737K
代理商： OR4E02-2BM680I
Lattice Semiconductor
49
Data Sheet
November, 2002
ORCA
Series 4 FPGAs
Microprocessor Interface (MPI)
The Series 4 FPGAs have a dedicated synchronous
MPI function block. The MPI is programmable to oper-
ate with
PowerPC
/PowerQUICC MPC860/MPC8260
series microprocessors. The MPI implements an 8-,
16-, or 32-bit interface with 1-bit, 2-bit, or 4-bit parity to
the host processor (
PowerPC
) that can be used for
con
fi
guration and readback of the FPGA as well as for
user-de
fi
ned data processing and general monitoring
of FPGA functions. In addition to dedicated-function
registers, the MPI bridges to the
AMBA
embedded sys-
tem bus through which the
PowerPC
bus master can
access the FPGA con
fi
guration logic, EBR and other
user logic. There is also capability to interrupt the host
processor either by a hard interrupt or by having the
host processor poll the MPI and the embedded system
bus.
The control portion of the MPI is available following
powerup of the FPGA if the mode pins specify MPI
mode, even if the FPGA is not yet con
fi
gured. The
width of the data port is selectable among 8-, 16-, or
32-bit and the parity bus can be 1-, 2-, or 4-bit. In con-
fi
guration mode the data and parity bus width are
related to the state of the M[0:3] mode pins. For post-
con
fi
guration use, the MPI must be included in the con-
fi
guration bit stream by using an MPI library element in
your design from the
ORCA
macro library, or by setting
the bit of the MPI con
fi
guration control register prior to
the start of con
fi
guration. The user can also enable and
disable the parity bus through the con
fi
guration bit
stream. These pads can be used as general I/O when
they are not needed for MPI use.
Table 22 shows the interface signals that are used to
interface Series 4 devices to a
PowerPC
MPC860/
MPC8260 device. More information is available in the
Series 4 MPI and System Bus application note.
The
ORCA
FPGA is a memory-mapped peripheral to
the
PowerPC
processor. The MPI interfaces to the
user-programmable FPGA logic using the
AMBA
embedded system bus.The MPI has access to a series
of addressable registers made accessible by the
AMBA
system bus that provide MPI control and status, con
fi
g-
uration and readback data transfer, FPGA device iden-
ti
fi
cation, and a dedicated user scratchpad register. All
registers are 8 bits wide. The address map for these
registers and the user-logic address space utilize the
same registers as the
AMBA
embedded system bus.
Embedded System Bus (ESB)
Implemented using the open standard, on-chip
AMBA
-
AHB 2.0 speci
fi
cation bus, the Series 4 devices con-
nects all the FPGA elements together with a standard-
ized bus framework. The ESB facilitates
communication among MPI, con
fi
guration, EBRs, and
user logic in all the generic FPGA devices. AHB serves
the need for high-performance
system-on-chip
(SoC) as well as aligning with current synthesis design
fl
ows. Multiple bus masters optimizes system perfor-
mance by sharing resources between different bus
masters such as the MPI and con
fi
guration logic. The
wide data bus con
fi
guration of 32-bits with 4-bit parity
supports the high-bandwidth of data-intensive applica-
tions of using the wide on-chip memory.
AMBA
enhances a reusable design methodology by de
fi
ning a
common backbone for IP modules.
The ESB is a synchronous bus that is driven by either
the MPI clock, internal oscillator, CCLK (slave con
fi
gu-
ration modes), TCK (JTAG con
fi
guration modes), or by
a user clock from routing. In FPSCs, a clock from the
embedded block can also drive the MPI clock. During
initial con
fi
guration and recon
fi
guration the bus clock is
defaulted to the con
fi
guration clock. The post con
fi
gu-
ration clock source is set during con
fi
guration. The user
has the ability to program several slaves through the
user logic interface. Embedded block RAM also inter-
faces seamlessly to the system bus.
A single bus arbiter controls the traf
fi
c on the bus by
ensuring only one master has access to the bus at any
time. The arbiter monitors a number of different
requests to use the bus and decides which request is
currently the highest priority. The con
fi
guration modes
have the highest priority and overrides all normal user
modes. Priority can be programmed between MPI and
user logic at con
fi
guration in generic FPGAs. If no pri-
ority is set a round-robin approach is used by granting
the next requesting master in a rotating
fi
xed order.
Several interfaces exist between the ESB and other
FPGA elements. The MPI interface acts as a bridge
between the external microprocessor bus and ESB.
The MPI may work in an independent clock domain
from the ESB if the ESB clock is not sourced from the
external microprocessor clock. Pipelined operation
allows high-speed memory interface to the EBR and
peripheral access without the requirement for addi-
tional cycles on the bus. Burst transfers allow optimal
use of the memory interface by giving advance infor-
mation of the nature of the transfers.
Table 23 is a listing of the ESB register
fi
le and brief
descriptions. Table 24 shows the system interrupt reg-
isters and Table 25 and Table 26 show the FPGA status
and command registers, all with brief descriptions.
More information is available in the Series 4 MPI and
System Bus application note.
相關(guān)PDF資料
PDF描述
OR4E02-3BA352C FPGA
OR4E02-3BM416C FPGA
OR4E02-3BM680C FPGA
OR4E04-1BA352C FPGA
OR4E04-1BA352I FPGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
OR4E02-3BA352C 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR4E02-3BM416C 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR4E02-3BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR4E04 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:ORCASeries 4 FPGAs
OR4E04-1BA3521 制造商:Rochester Electronics LLC 功能描述: 制造商:Lattice Semiconductor Corporation 功能描述:
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