參數(shù)資料
型號： OR4E02-2BM680I
英文描述： FPGA
中文描述： FPGA的
文件頁數(shù)： 101/153頁
文件大?。?/td> 2737K
代理商： OR4E02-2BM680I
Lattice Semiconductor
101
Data Sheet
November, 2002
ORCA
Series 4 FPGAs
Pin Information
Pin Descriptions
This section describes the pins found on the Series 4 FPGAs. Any pin not described in this table is a user-program-
mable I/O. During con
fi
guration, the user-programmable I/Os are 3-stated with an internal pull-up resistor enabled.
If any pin is not used (or not bonded to a package pin), it is also 3-stated with an internal pull-up resistor enabled
after con
fi
guration. The pin descriptions in Table 65 and throughout this data sheet show active-low signals with an
overscore. The package pinout tables that follow, show this as a signal ending with _N, for LDC and LDC_N are
equivalent.
Table 65. Pin Descriptions
Symbol
I/O
Description
Dedicated Pins
V
DD
33
— 3.3 V positive power supply. This power supply is used for 3.3 V con
fi
guration RAMs and
internal PLLs. When using PLLs, this power supply should be well isolated from all other
power supplies on the board for proper operation.
— 1.5 V positive power supply for internal logic.
— Positive power supply used by I/O banks.
— Ground.
I
Temperature sensing diode pin. Dedicated input.
I
During con
fi
guration,
RESET
forces the restart of con
fi
guration and a pull-up is enabled.
After con
fi
guration,
RESET
can be used as a general FPGA input or as a direct input,
which causes all PLC latches/FFs to be asynchronously set/reset.
O
In the master and asynchronous peripheral modes, CCLK is an output which strobes con-
fi
guration data in.
I
In the slave or readback after con
fi
guration, CCLK is input synchronous with the data on
DIN or D[7:0]. CCLK is an output for daisy-chain operation when the lead device is in
master, peripheral, or system bus modes.
I
As an input, a low level on DONE delays FPGA start-up after con
fi
guration.*
O
As an active-high, open-drain output, a high level on this signal indicates that con
fi
gura-
tion is complete. DONE has an optional pull-up resistor.
I
PRGM
is an active-low input that forces the restart of con
fi
guration and resets the bound-
ary-scan circuitry. This pin always has an active pull-up.
I
This pin must be held high during device initialization until the
INIT
pin goes high. This pin
always has an active pull-up.
During con
fi
guration,
RD_CFG
is an active-low input that activates the TS_ALL function
and 3-states all of the I/O.
After con
fi
guration,
RD_CFG
can be selected (via a bit stream option) to activate the
TS_ALL function as described above, or, if readback is enabled via a bit stream option, a
high-to-low transition on
RD_CFG
will initiate readback of the con
fi
guration data, including
PFU output states, starting with frame address 0.
O
RD_DATA/TDO is a dual-function pin. If used for readback, RD_DATA provides con
fi
gura-
tion data out. If used in boundary-scan, TDO is test data out.
O
During JTAG, slave, master, and asynchronous peripheral con
fi
guration assertion on this
CFG_IRQ
(active-low) indicates an error or errors for block RAM or FPSC initialization.
MPI
active-low interrupt request output, when the MPI is used.
V
DD
15
V
DD
IO
V
SS
PTEMP
RESET
CCLK
DONE
PRGM
RD_CFG
RD_DATA/TDO
CFG_IRQ/MPI_IRQ
* The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE release
is controlled by one set of bit stream options, and the timing of the simultaneous release of all other con
fi
guration pins (and the activation of all
user I/Os) is controlled by a second set of options.
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