參數(shù)資料
型號： OR4E02-2BM680I
英文描述： FPGA
中文描述： FPGA的
文件頁數(shù)： 11/153頁
文件大?。?/td> 2737K
代理商： OR4E02-2BM680I
Lattice Semiconductor
11
Data Sheet
November, 2002
ORCA
Series 4 FPGAs
Programmable Logic Cells
(continued)
Logic Mode
The PFU diagram of Figure 3 represents the logic
mode of operation. In logic mode, the eight LUTs are
used individually or in
fl
exible groups to implement user
logic functions. The latches/FFs may be used in con-
junction with the LUTs or separately with the direct
PFU data inputs. There are three basic submodes of
LUT operation in PFU logic mode: F4 mode, F5 mode,
and the F6 mode. Combinations of the submodes are
possible in each PFU.
F4 mode, shown simpli
fi
ed in Figure 4, illustrates the
uses of the basic 4-input LUTs in the PFU. The output
of an F4 LUT can be passed out of the PFU, captured
at the LUTs associated latch/FF, or multiplexed with the
adjacent F4 LUT output using one of the F5[A:D] inputs
to the PFU. Only adjacent LUT pairs (K
and K
3
, K
4
and K
5
, K
6
and K
the output always goes to the even-numbered output of
the pair.
0
and K
1
, K
2
7
) can be multiplexed, and
The F5 submode of the LUT operation, shown simpli-
fi
ed in Figure 4, indicates the use of 5-input LUTs to
implement logic. 5-input LUTs are created from two
4-input LUTs and a multiplexer. The F5 LUT is the
same as the multiplexing of two F4 LUTs described
previously with the constraint that the inputs to the F4
LUTs be the same. The F5[A:D] input is then used as
the
fi
fth LUT input. The equations for the two F4 LUTs
will differ by the assumed value for the F5[A:D] input,
one F4 LUT assuming that the F5[A:D] input is zero,
and the other assuming it is a one. The selection of the
appropriate F4 LUT output in the F5 MUX by the
F5[A:D] signal creates a 5-input LUT. Any combination
of F4 and F5 LUTs is allowed per PFU using the eight
16-bit LUTs. Examples are eight F4 LUTs, four F5
LUTs, and a combination of four F4 plus two F5 LUTs.
Two 6-input LUTs are created by shorting together the
input of four 4-input LUTs (K0:3 and K4:7) which are
multiplexed together. The F5 inputs of the adjacent F4
LUTs derive the
fi
fth and sixth inputs of the F6 mode.
The F6 outputs, LUT603 and LUT647, are dedicated to
the F6 mode or can be used as the outputs of
MUX8x1. MUX8x1 modes are created by programming
adjacent 4-input LUTs to 2x1 MUXs and multiplexing
down to create MUX8x1. Both F6 mode and MUX8x1
are available in the upper and lower PFU nibbles.
5-9733(F)
Figure 4. Simpli
fi
ed F4 and F5 Logic Modes
K7_0
K7_1
K7_2
K7_3
F5D
LUT4
LUT4
2x1
MUX
F6
K6_0
K6_1
K6_2
K6_3
K5_0
K5_1
K5_2
K5_3
F5C
LUT4
LUT4
2x1
MUX
F4
K4_0
K4_1
K4_2
K4_3
K3_0
K3_1
K3_2
K3_3
F5B
LUT4
LUT4
2x1
MUX
F2
K2_0
K2_1
K2_2
K2_3
K1_0
K1_1
K1_2
K1_3
F5A
LUT4
LUT4
2x1
MUX
F0
K0_0
K0_1
K0_2
K0_3
K7
F7
K6
F6
K5
F5
K4
F4
K3
F3
K2
F2
K1
F1
K0
F0
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OR4E02-3BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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OR4E04-1BA3521 制造商:Rochester Electronics LLC 功能描述: 制造商:Lattice Semiconductor Corporation 功能描述:
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