參數(shù)資料
型號(hào): OR4E02-2BM680I
英文描述: FPGA
中文描述: FPGA的
文件頁數(shù): 52/153頁
文件大小: 2737K
代理商: OR4E02-2BM680I
52
Lattice Semiconductor
Data Sheet
November, 2002
ORCA
Series 4 FPGAs
Microprocessor Interface
(continued)
Table 25. Status Register Space Assignments
Notes: RO = Read Only. For internal system bus, bit 7 is most signi
fi
cant bit, for MPI bit 0 is most signi
fi
cant bit.
Table 26. Command Register Space Assignments
Note: R/W = Read/Write. For internal system bus; bit 7 is most signi
fi
cant bit, for MPI bit 0 is most signi
fi
cant bit.
Byte
0F
0E
OD
bit
7:0
7:0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Read/Write
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Description
Reserved
Reserved
Con
fi
guration Write Data Acknowledge
Readback Data Ready
Unassigned (Zero)
Unassigned (Zero)
FPSC_BIT_ERR
RAM_BIT_ERR
Con
fi
guration Write Data Size (1, 2, or 4 bytes)
Use with above for HSIZE[1:0] (byte, half-word, word)
Readback Addresses Out of Range
Error Response Received by CFG From System Bus
Error Responses Received by CFG From System Bus
CFG_DATA_LOST
DONE
INIT_N
ERR_FLAG 1
ERR_FLAG 0
0C
Byte
0B
0A
09
bit
7:0
7:0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
Reserved
SYS_GSR (GSR Input)
SYS_RD_CFG (similar to FPGA pin RD_CFGN, but active high)
PRGM from MPI > (similar to FPGA pin, but active high)
PRGM from USER > (similar to FPGA pin, but active high)
PRGM from FPSC > (similar to FPGA pin, but active high)
LOCK from MPI
LOCK from USER
LOCK from FPSC
Bus Reset from MPI (resets system bus and registers)
Bus Reset from USER (resets system bus and registers)
Bus Reset from FPSC (resets system bus and registers)
SYS_DAISY
REPEAT_RDBK (don't increment readback address)
MPI_USR_ENABLE
Readback Data Size (1, 2, or 4 bytes)
Use with above for HSIZE[1:0]
08
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