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| 型號： | OR4E02-2BM680I |
| 英文描述： | FPGA |
| 中文描述： | FPGA的 |
| 文件頁數(shù)： | 26/153頁 |
| 文件大小： | 2737K |
| 代理商： | OR4E02-2BM680I |
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26
Lattice Semiconductor
Data Sheet
November, 2002
ORCA
Series 4 FPGAs
Embedded Block RAM (EBR)
The
ORCA
Series 4 devices compliment the distributed
PFU RAM with large blocks of memory macrocells. The
memory is available in 512 words by 18 bits/word
blocks with 2 read and 2 write ports with two byte lane
enables which operate with quad-port functionality.
Additional logic has been incorporated for FIFO, multi-
plier, and CAM implementations. The RAM blocks are
organized along the PLC rows and are added in pro-
portion to the FPGA array sizes as shown in Table 7.
The contents of the RAM blocks may be optionally ini-
tialized during FPGA con
fi
guration.
Table 7.
ORCA
Series 4— Available Embedded
Block RAM
Each highly
fl
exible 512x18 (quad-port, two read/two
write) RAM block can be programmed by the user to
meet their particular function. Each of the EBR con
fi
gu-
rations use the physical signals as shown in
Table 8. Quad-port addressing permits simultaneous
read and write operations on all four ports.
The EBR ports are written synchronously on the posi-
tive-edge of CKW. Synchronous read operations uses
the positive-edge of CKR. Options are available to use
synchronous read address registers and read output
registers, or to bypass these registers and have the
RAM read operate asynchronously. Detailed informa-
tion about the EBR blocks is found in various applica-
tion notes.
ispLEVER provides SCUBA as a RAM generation tool
for EBR RAMs. Many of the EBR sub-modes are sup-
ported and the initialization values can also be de
fi
ned.
EBR Features
Quad Port RAM Modes (Two Read/Two Write)
■
One 512 x 18 RAM with optional built-in write arbitra-
tion.
■
One 1024 x 18 RAM built on two blocks with built-in
decode logic for simpli
fi
ed implementation.
Dual Port RAM Modes (One Read/One Write)
■
One 256 x 36 RAM.
■
One 1K x 9 RAM.
■
Two independent 512 x 9 RAMs built in one EBR with
separate read clocks, write clocks and enables.
■
Two independent RAMS with arbitrary number of
words whose sum is 512 words or less by 18 bits/
word or less.
The joining of RAM blocks is supported to create wider
deeper memories. The adjacent routing interface pro-
vided by the CIBs allow the cascading of blocks
together with minimal penalties due to routing delays.
It is also possible to connect any or all of the EBR RAM
blocks together through the embedded system bus,
which is discussed in a later section of this data sheet.
Arbitration logic is optionally programmed by the user
to signal occurrences of data collisions as well as to
block both ports from writing at the same time. The
arbitration logic prioritizes PORT1. When utilizing the
arbiter, the signal BUSY indicates data is being written
to PORT1. This BUSY output signals PORT1 activity by
driving a high output. If the arbiter is turned off both
ports could be written at the same time and the data
would be corrupt. In this scenario the BUSY signal will
indicate a possible error.
There is also a user option which dedicates PORT 1 to
communications to the system bus. In this mode the
user logic only has access to PORT0 and arbitration
logic is enabled. The system bus utilizes the priority
given to it by the arbiter therefore the system bus will
always be able to write to the EBR.
Device
Number of
Blocks
8
12
16
Number of
EBR Bits
74K
111K
147K
OR4E02
OR4E04
OR4E06
相關PDF資料 |
PDF描述 |
|---|---|
| OR4E02-3BA352C | FPGA |
| OR4E02-3BM416C | FPGA |
| OR4E02-3BM680C | FPGA |
| OR4E04-1BA352C | FPGA |
| OR4E04-1BA352I | FPGA |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| OR4E02-3BA352C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR4E02-3BM416C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR4E02-3BM680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR4E04 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:ORCASeries 4 FPGAs |
| OR4E04-1BA3521 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Lattice Semiconductor Corporation 功能描述: |
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