參數(shù)資料
型號： OR4E02-2BM680I
英文描述： FPGA
中文描述： FPGA的
文件頁數(shù)： 62/153頁
文件大小： 2737K
代理商： OR4E02-2BM680I
62
Lattice Semiconductor
Data Sheet
November, 2002
ORCA
Series 4 FPGAs
Con
fi
guration Data Format
(continued)
Con
fi
guration Data Frame
Con
fi
guration data can be presented to the FPGA in two frame formats: autoincrement and explicit. A detailed
description of the frame formats is shown in Figure 36, Figure 37, and Tables Table 31 and Table 31A. The two
modes are similar except that autoincrement mode uses assumed address incrementation to reduce the bit stream
size, and explicit mode uses an optional address frame. In both cases, the header frame begins with a series of 1s
and a preamble of 0010, followed by a 24-bit length count
fi
eld representing the total number of con
fi
guration
clocks needed to complete the loading of the FPGAs. If only Series 4 devices are used, a second preamble value
of 0100 is supported. If this preamble is found, the Series 4 device will expect an expanded length count
fi
eld of 32-
bits. This allows more larger Series 4 FPGAs to be con
fi
gured through daisy-chaining.
Following the header frame is a mandatory ID frame. The ID frame contains data used to determine if the bit
stream is being loaded to the correct type of
ORCA
FPGA (i.e., a bit stream generated for an OR4E06 is being sent
to an OR4E06). Error checking is always enabled for Series 4 devices through the use of an 8-bit checksum. Fol-
lowing the ID frame is a 16-bit header to select the portion of the device to be con
fi
gured with the following data. the
options are an FPGA header (shown in Table 32), an embedded RAM header (shown in Table 32A), and an FPSC
embedded block header (not shown).
A con
fi
guration data frame follows the header frame. A data frame starts with a 01-start bit pair and ends with
enough 1-stop bit to reach a byte boundary. If subsequent data frames follow the frame address is auto-incre-
mented. If using explicit mode, an address frame can follow a data frame, telling the FPGA at what address to
update the auto-increment counter to for the next data frame. Address frame starts with 00.
Following all data and address frames is the postamble. The format of the postamble is the same as an address
frame with the highest possible address value with the checksum set to all ones, if no other sections of con
fi
gura-
tion data follow. If another section is to follow, the header starts with 10.
5-5759(F)
Figure 36. Serial Con
fi
guration Data Format—Autoincrement Mode
5-5760(F).a
Figure 37. Serial Con
fi
guration Data Format—Explicit Mode
CONFIGURATION DATA
CONFIGURATION DATA
1 0
0 1
0 1
PREAMBLE LENGTH
ID FRAME
CONFIGURATION
DATA FRAME 1
CONFIGURATION
DATA FRAME 2
POSTAMBLE
CONFIGURATION HEADER
0 0
0 0
COUNT
PREAMBLE COUNT
ID FRAME
CONFIGURATION
DATA FRAME 1
CONFIGURATION
DATA FRAME 2
POSTAMBLE
CONFIGURATION HEADER
ADDRESS
FRAME 1
0 0
CONFIGURATION DATA
CONFIGURATION DATA
1 0
0 1
0 1
0 0
0 0
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OR4E02-3BA352C 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR4E02-3BM416C 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR4E02-3BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR4E04 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:ORCASeries 4 FPGAs
OR4E04-1BA3521 制造商:Rochester Electronics LLC 功能描述: 制造商:Lattice Semiconductor Corporation 功能描述:
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