參數(shù)資料
型號(hào)： OR4E02-2BM680I
英文描述： FPGA
中文描述： FPGA的
文件頁(yè)數(shù)： 53/153頁(yè)
文件大?。?/td> 2737K
代理商： OR4E02-2BM680I
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Lattice Semiconductor
53
Data Sheet
November, 2002
ORCA
Series 4 FPGAs
Phase-Locked Loops (PLLs)
There are eight PLLs available to perform many clock modi
fi
cation and clock conditioning functions on the Series 4
FPGAs. Six of the PLLs are programmable allowing the user the
fl
exibility to con
fi
gure the PLL to manipulate the
frequency, phase, and duty cycle of a clock signal. Four of the programmable PLLs (PPLLs) are capable of manipu-
lating and conditioning clocks from 15 MHz to 200 MHz and two others (HPPLLs) are capable of manipulating and
conditioning clocks from 60 MHz to 420 MHz. Frequencies can be adjusted from 1/64x to 64x the input clock fre-
quency. Each programmable PLL provides two outputs that have different multiplication factors with the same
phase relationships. Duty cycles and phase delays can be adjusted in 12.5% of the clock period increments. An
automatic delay compensation mode is available for phase delay. Each PPLL and HPPLL provides two outputs that
can have programmable (45 degree increments) phase differences.
The PPLLs and HPPLLs can be utilized to eliminate skew between the clock input pad and the internal clock inputs
across the entire device. Both the PPLLS or the HPPLLs can drive onto the primary and secondary clock networks
inside the FPGA. Each can take a clock input from the dedicated pad or differential pair of pads in its corner or from
general routing resources.
Functionality of the PPLLs and HPPLLs is programmed during operation through a control register internal to the
FPGA array or via the con
fi
guration bit stream. The embedded system bus enables access to these registers (see
Table 23). There is also a PLL output signal, LOCK, that indicates a stable output clock state.
Table 27. PPLL Speci
fi
cations
Additional highly tuned and characterized dedicated phase-locked loops (DPLLs) are included to ease system
designs. These DPLLs meet ITU-T G.811 primary clocking speci
fi
cations and enable system designers to target
very tightly speci
fi
ed clock conditioning not available in the programmable PPLLs. They also provide enhanced jitter
fi
ltering to reduce the amount of input jitter that is transferred to the PLL output when used in any application.
DPLLs are targeted to low-speed DS1 and E1 networking systems (PLL1) and high-speed SONET/SDH network-
ing STS-3 and STM-1 networking systems (PLL2).
Parameter
Min
1.425
3.0
–40
2.0
7.5
15
60
30
45
—
Nom
1.5
3.3
—
—
—
—
—
—
50
<50
Up to 64x
Down to 1/64x
Max
1.575
3.6
125
200
420
200
420
70
55
—
Unit
V
V
C
MHz
V
DD
15
V
DD
33
Operating Temp
Input Clock Frequency
(No division)
Output Clock Frequency
PPLL
HPPLL
PPLL
HPPLL
MHz
Input Duty Cycle
Output Duty Cycle
Lock Time
Frequency Multiplication
Frequency Division
Duty Cycle Adjust of Output Clock
Delay Adjust of Output Clock
Phase Shift Between MCLK and NCLK
%
%
μs
—
—
%
12.5, 25, 37.5, 50, 62.5, 75, 87.5
0, 45, 90, 135, 180, 225, 270, 315
0, 45, 90, 135, 180, 225, 270, 315
degrees
degrees
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OR4E02-3BA352C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR4E02-3BM416C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR4E02-3BM680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR4E04 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:ORCASeries 4 FPGAs
OR4E04-1BA3521 制造商:Rochester Electronics LLC 功能描述: 制造商:Lattice Semiconductor Corporation 功能描述:
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