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| 型號(hào)： | OR4E02-2BM680I |
| 英文描述： | FPGA |
| 中文描述： | FPGA的 |
| 文件頁(yè)數(shù)： | 6/153頁(yè) |
| 文件大?。?/td> | 2737K |
| 代理商： | OR4E02-2BM680I |
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6
Lattice Semiconductor
Data Sheet
November, 2002
ORCA
Series 4 FPGAs
Product Description
(continued)
Note: For FPSCs, all I/Os and the four PLLs on the right side of the device are replaced with the embedded core.
5-7536(F)a
Figure 1. Series 4 Top Level Diagram
Programmable Logic Cells
The PLCs are arranged in an array of rows and columns. The location of a PLC is indicated by its row and column
so that a PLC in the second row and the third column is R2C3. The array of actual PLCs for every device begins
with R3C2 in all Series 4 generic FPGAs. PIOs are located on all four sides of the FPGA. Every group of four PIOs
on the device edge have an associated PIC.
The PLC consists of a PFU, SLIC, and routing resources. Each PFU within a PLC contains eight
4-input (16-bit) LUTs, eight latches/FFs, and one additional FF that may be used independently or with arithmetic
functions. The PFU is the main logic element of the PLC, containing elements for both combinatorial and sequential
logic. Combinatorial logic is done in LUTs located in the PFU. The PFU can be used in different modes to meet dif-
ferent logic requirements. The LUTs twin-quad architecture provides a con
fi
gurable medium-/large-grain architec-
ture that can be used to implement from one to eight independent combinatorial logic functions or a large number
of complex logic functions using multiple LUTs. The
fl
exibility of the LUT to handle wide input functions, as well as
multiple smaller input functions, maximizes the gate count per PFU while increasing system speed.
The PFU is organized in a twin-quad fashion: two sets of four LUTs and FFs that can be controlled independently.
Each PFU has two independent programmable clocks, clock enables, local set/reset, and data selects.
LUTs may also be combined for use in arithmetic functions using fast-carry chain logic in either 4-bit or 8-bit
modes. The carry-out of either mode may be registered in the ninth FF for pipelining. Each PFU may also be con-
fi
gured as a synchronous 32x4 single- or dual-port RAM or ROM. The FFs (or latches) may obtain input from LUT
outputs or directly from invertible PFU inputs, or they can be tied high or tied low. The FFs also have programmable
clock polarity, clock enables, and local set/reset.
EMBEDDED
SYSTEM BUS
P
PLC
MICROPROCESSOR
INTERFACE (MPI)
PFU
SLIC
FPGA/SYSTEM
BUS INTERFACE
PLLs
(ALL 4
EMBEDDED
BLOCK RAM
HIGH-SPEED I/Os
CLOCK PINS
(ALL 4 SIDES)
PIO
REPLACED BY
EMBEDDED IP
CORE FOR FPSCs
CORNERS)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OR4E02-3BA352C | FPGA |
| OR4E02-3BM416C | FPGA |
| OR4E02-3BM680C | FPGA |
| OR4E04-1BA352C | FPGA |
| OR4E04-1BA352I | FPGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR4E02-3BA352C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR4E02-3BM416C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR4E02-3BM680C | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR4E04 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:ORCASeries 4 FPGAs |
| OR4E04-1BA3521 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Lattice Semiconductor Corporation 功能描述: |
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