參數(shù)資料
型號： OR4E02-2BM680I
英文描述： FPGA
中文描述： FPGA的
文件頁數(shù)： 24/153頁
文件大小： 2737K
代理商： OR4E02-2BM680I
24
Lattice Semiconductor
Data Sheet
November, 2002
ORCA
Series 4 FPGAs
Programmable Logic Cells
(continued)
5-5748(F)
Figure 19. Decoder Mode
PLC Latches/Flip-Flops
The eight general-purpose latches/FFs in the PFU can
be used in a variety of con
fi
gurations. In some cases,
the con
fi
guration options apply to all eight latches/FFs
in the PFU and some apply to the latches/FFs on a nib-
ble-wide basis where the ninth FF is considered inde-
pendently. For other options, each latch/FF is
independently programmable. In addition, the ninth FF
can be used for a variety of functions.
Table 6 summarizes these latch/FF options. The
latches/FFs can be con
fi
gured as either positive- or
negative-level sensitive latches, or positive or negative
edge-triggered FFs (the ninth register can only be a
FF). All latches/FFs in a given PFU share the same
clock, and the clock to these latches/FFs can be
inverted. The input into each latch/FF is from either the
corresponding LUT output (F[7:0]) or the direct data
input (DIN[7:0]). The latch/FF input can also be tied to
logic 1 or to logic 0, which is the default.
Table 6. Con
fi
guration RAM Controlled Latch/
Flip-Flop Operation
Each PFU has two independent programmable clocks,
clock enable CE[1:0], local set/reset LSR[1:0], and
front end data selects SEL[1:0]. When CE is disabled,
each latch/FF retains its previous value when clocked.
The clock enable, LSR, and SEL inputs can be inverted
to be active-low.
DEC
SIN7
LOGIC 1 OR 0
SIN6
LOGIC 1 OR 0
SIN5
LOGIC 1 OR 0
SIN4
LOGIC 1 OR 0
SIN9
LOGIC 1 OR 0
SIN8
LOGIC 1 OR 0
SIN3
LOGIC 1 OR 0
SIN1
LOGIC 1 OR 0
SIN2
LOGIC 1 OR 0
SIN0
LOGIC 1 OR 0
Function
Common to All Latches/FFs in PFU
LSR Operation
Asynchronous or synchronous.
Clock Polarity
Noninverted or inverted.
Front-end Select* Direct (DIN[7:0]) or from LUT
(F[7:0]).
LSR Priority
Either LSR or CE has priority.
Latch/FF Mode
Latch or FF.
Enable GSRN
GSRN enabled or has no effect on
PFU latches/FFs.
Set Individually in Each Latch/FF in PFU
Set/Reset Mode
Set or reset.
By Group (Latch/FF[3:0], Latch/FF[7:4], and FF[8])
Clock Enable
CE or none.
LSR Control
LSR or none.
* Not available for FF[8].
Options
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