參數(shù)資料
型號： OR4E02-2BM680I
英文描述： FPGA
中文描述： FPGA的
文件頁數(shù)： 72/153頁
文件大小： 2737K
代理商： OR4E02-2BM680I
72
Lattice Semiconductor
Data Sheet
November, 2002
ORCA
Series 4 FPGAs
FPGA Con
fi
guration Modes
(continued)
Slave Serial Mode
The slave serial mode is primarily used when multiple FPGAs are con
fi
gured in a daisy-chain (see the Daisy-
Chaining section). It is also used on the FPGA evaluation board that interfaces to the download cable. A device in
the slave serial mode can be used as the lead device in a daisy-chain. Figure 44 shows the connections for the
slave serial con
fi
guration mode.
The con
fi
guration data is provided into the FPGA’s DIN input synchronous with the con
fi
guration clock CCLK input.
After the FPGA has loaded its con
fi
guration data, it retransmits the incoming con
fi
guration data on DOUT at the ris-
ing edge of CCLK. CCLK is routed into all slave serial mode devices in parallel.
Multiple slave FPGAs can be loaded with identical con
fi
gurations simultaneously. This is done by loading the con-
fi
guration data into the DIN inputs in parallel.
5-4485(F).a
Figure 44. Slave Serial Con
fi
guration Schematic
Slave Parallel Mode
The slave parallel mode is essentially the same as the slave serial mode except that 8 bits of data are input on pins
D[7:0] for each CCLK cycle. Due to 8 bits of data being input per CCLK cycle, the DOUT pin does not contain a
valid bit stream for slave parallel mode. As a result, the lead device cannot be used in the slave parallel mode in a
daisy-chain con
fi
guration.
Figure 45
is a schematic of the connections for the slave parallel con
fi
guration mode. WR and CS0 are active-low
chip select signals, and CS1 is an active-high chip select signal. These chip selects allow the user to con
fi
gure mul-
tiple FPGAs in slave parallel mode using an 8-bit data bus common to all of the FPGAs. These chip selects can
then be used to select the FPGAs to be con
fi
gured with a given bit stream. The chip selects must be active for each
valid CCLK cycle until the device has been completely programmed. They can be inactive between cycles but must
meet the setup and hold times for each valid positive CCLK. D[7:0] of the FPGA can be connected to D[7:0] of the
microprocessor only if a standard prom
fi
le format is used. If a .bit or .rbt
fi
le is used from ispLEVER, then the user
must mirror the bytes in the .bit or .rbt
fi
le OR leave the .bit or .rbt
fi
le unchanged and connect D[7:0] of the FPGA
to D[0:7] of the microprocessor.
MICRO-
PROCESSOR
OR
DOWNLOAD
CABLE
M2
M1
M0
HDC
SERIES
FPGA
LDC
V
DD
CCLK
PRGM
DOUT
TO DAISY-
CHAINED
DEVICES
DONE
DIN
INIT
ORCA
M3
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相關代理商/技術參數(shù)
參數(shù)描述
OR4E02-3BA352C 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
OR4E02-3BM416C 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
OR4E02-3BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 4992 LUT 405 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
OR4E04 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:ORCASeries 4 FPGAs
OR4E04-1BA3521 制造商:Rochester Electronics LLC 功能描述: 制造商:Lattice Semiconductor Corporation 功能描述:
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