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| 型號(hào)： | OR3L225B |
| 廠商： | Lineage Power |
| 英文描述： | Field-Programmable Gate Arrays(現(xiàn)場(chǎng)可編程門陣列) |
| 中文描述： | 現(xiàn)場(chǎng)可編程門陣列（現(xiàn)場(chǎng)可編程門陣列） |
| 文件頁數(shù)： | 9/88頁 |
| 文件大?。?/td> | 2015K |
| 代理商： | OR3L225B |
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Lucent Technologies Inc.
9
Data Addendum
December 1999
ORCA OR3LxxxB Series FPGAs
Description
(continued)
System Features
The OR3LxxxB Series also provides system-level func-
tionality by means of its dual-use MPI and its innovative
PCM. These functional blocks allow for easy glueless
system interfacing and the capability to adjust to vary-
ing conditions in today’s high-speed systems.
The MPI provides a glueless interface between the
FPGA, PowerPC, and i960microprocessors. It can be
used for configuration and readback, as well as for
monitoring FPGA status. The MPI also provides a gen-
eral-purpose microprocessor interface to the FPGA
user-defined logic following configuration.
Two PCMs are provided on each ORCA 3L device.
Each PCM can be used to manipulate the frequency,
phase, and duty cycle of a clock signal. Clocks may be
input from the dedicated corner ExpressCLK input (in
the same corner as the PCM block) or from general
routing. Output clocks from the PCM can be sent to the
system clock spines, and/or to the ExpressCLK and
fast clock spines on the edges of the device adjacent to
the PCM. ExpressCLK/fast clock and system clock out-
put frequencies can differ by up to a factor of eight to
allow slow I/O clocking with fast internal processing (or
vice versa). Each PCM is capable of manipulating
clocks from 5 MHz to 120 MHz. Frequencies can be
adjusted from 1/8
×
to 64
×
the input clock frequency,
duty cycles, and phase delays can be adjusted from
3.125% to 96.875%.
Routing
The abundant routing resources of the ORCA3LxxxB
FPGAs are organized to route signals individually or as
buses with related control signals. Clocks are routed
on a low-skew, high-speed distribution network and
may be sourced from PLC logic, externally from any
I/O pad, or from the very fast ExpressCLK pins.
ExpressCLKs may be glitchlessly and independently
enabled and disabled with a programmable control sig-
nal using the new StopCLK feature. The improved PIC
routing resources are now similar to the patented intra-
PLC routing resources and provide great flexibility in
moving signals to and from the PIOs. This flexibility
translates into an improved capability to route designs
at the required speeds when the I/O signals have been
locked to specific pins.
Configuration
The FPGA’s functionality is determined by internal con-
figuration RAM. The FPGA’s internal initialization/con-
figuration circuitry loads the configuration data at
powerup or under system control. The RAM is loaded
by using one of several configuration modes. The con-
figuration data resides externally in an EEPROM or
any other storage media. Serial EEPROMs provide a
simple, low pin count method for configuring FPGAs. A
new, easy method for configuring the devices is
through the microprocessor interface.
Configuration Data Format
The length and number of data frames and information on the PROM size for the Series OR3LxxxB FPGAs are
given in Table 3.
Table 3. Configuration Frame Size
Devices
3L165B
2136
502
1,072,272
3L225B
2520
592
1,552,320
Number of Frames
Data Bits/Frame
Configuration Data
(number of frames
×
number of data bits/frame)
Maximum Total Number Bits/Frame
(align bits, 01 frame start, 8-bit checksum, eight stop bits)
Maximum Configuration Data
(number bits/frame
×
number of frames)
Maximum PROM Size (bits)
(add configuration header and postamble)
520
610
1,110,720
1,537,200
1,110,760
1,537,240
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