參數(shù)資料
型號(hào)： OR3L225B
廠商： Lineage Power
英文描述： Field-Programmable Gate Arrays(現(xiàn)場(chǎng)可編程門陣列)
中文描述： 現(xiàn)場(chǎng)可編程門陣列（現(xiàn)場(chǎng)可編程門陣列）
文件頁(yè)數(shù)： 8/88頁(yè)
文件大小： 2015K
代理商： OR3L225B
8
Lucent Technologies Inc.
Data Addendum
December 1999
ORCA OR3LxxxB Series FPGAs
Description
(continued)
PIC Logic
The OR3LxxxB PIC addresses the demand for ever-
increasing system clock speeds. Each PIC contains
four programmable inputs/outputs (PIOs) and routing
resources. On the input side, each PIO contains a fast-
capture latch that is clocked by an ExpressCLK. This
latch is followed by a latch/FF that is clocked by a sys-
tem clock from the internal general clock routing. The
combination provides for very low setup requirements
and zero hold times for signals coming on-chip. It may
also be used to demultiplex an input signal, such as a
multiplexed address/data signal, and register the sig-
nals without explicitly building a demultiplexer. Two
input signals are available to the PLC array from each
PIO, and the ORCA Series 2 capability to use any input
pin as a clock or other global input is maintained.
On the output side of each PIO, two outputs from the
PLC array can be routed to each output flip-flop, and
logic can be associated with each I/O pad. The output
logic associated with each pad allows for multiplexing
of output signals and other functions of two output sig-
nals.
The output FF, in combination with output signal multi-
plexing, is particularly useful for registering address
signals to be multiplexed with data, allowing a full clock
cycle for the data to propagate to the output. The I/O
buffer associated with each pad is very similar to the
Series 2 buffer with a new, fast, open-drain option for
ease of use on system buses. These features may also
be combined with the new 3-state FF that allows the
3-state control signal to be registered. This allows for
early control setup and faster clock-to-out times.
5-5805(F).a
Figure 3. OR3Lxxx Programmable Input/Output Image from ORCAFoundry
IN2
IN1
D0
D1
CK
SP
SD
LSR
INREGMODE
LATCHFF
LATCH
FF
D
CK
NORMAL
INVERTED
RESET
SET
LEVEL MODE
TTL
CMOS
UP
DOWN
NONE
PULL-MODE
BUFFER
MODE
TS
FAST
SLEW
SINK
RESET
SET
LSR
SP
CK
D
OUT1
OUT2
ECLK
SCLK
CE
CE_OVER_LSR
LSR_OVER_CE
ASYNC
LSR
ENABLE_GSR
DISABLE_GSR
OUT1OUTREG
OUT2OUTREG
OUT1OUT2
NOR
XOR
XNOR
AND
NAND
OR
PIO LOGIC
CLKIN
0
0
1
0
PAD
Q
Q
1
PD
T
Q
1
ECLK
SCLK
PMUX
F
LSR
CK
D0 Q
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